Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Processor Configuration Registers
50
Datasheet, Volume 2
2.5.4
PCISTS—PCI Status Register
This status register reports the occurrence of error events on Device 0's PCI interface.
Since Device 0 does not physically reside on PCI_A, many of the bits are not
implemented.
Since Device 0 does not physically reside on PCI_A, many of the bits are not
implemented.
1
RO
1b
Uncore
Memory Access Enable (MAE)
The processor always allows access to main memory, except when
The processor always allows access to main memory, except when
such access would violate security principles. Such exceptions are
outside the scope of PCI control. This bit is not implemented and is
hardwired to 1. Writes to this bit position have no effect.
0
RO
0b
Uncore
I/O Access Enable (IOAE)
This bit is not implemented in the processor and is hardwired to a
This bit is not implemented in the processor and is hardwired to a
0. Writes to this bit position have no effect.
B/D/F/Type:
0/0/0/PCI
Address Offset:
4–5h
Reset Value:
0006h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
00h
Bit
Attr
Reset
Value
RST/
PWR
Description
B/D/F/Type:
0/0/0/PCI
Address Offset:
6–7h
Reset Value:
0090h
Access:
RO, RW1C
Size:
16 bits
BIOS Optimal Default
00h
Bit
Attr
Reset
Value
RST/
PWR
Description
15
RW1C
0b
Uncore
Detected Parity Error (DPE)
This bit is set when this Device receives a Poisoned TLP.
This bit is set when this Device receives a Poisoned TLP.
14
RW1C
0b
Uncore
Signaled System Error (SSE)
This bit is set to 1 when Device 0 generates an SERR message over
This bit is set to 1 when Device 0 generates an SERR message over
DMI for any enabled Device 0 error condition. Device 0 error
conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK
registers. Device 0 error flags are read/reset from the PCISTS,
ERRSTS, or DMIUEST registers. Software clears this bit by writing
a 1 to it.
13
RW1C
0b
Uncore
Received Master Abort Status (RMAS)
This bit is set when the processor generates a DMI request that
This bit is set when the processor generates a DMI request that
receives an Unsupported Request completion packet. Software
clears this bit by writing a 1 to it.
12
RW1C
0b
Uncore
Received Target Abort Status (RTAS)
This bit is set when the processor generates a DMI request that
This bit is set when the processor generates a DMI request that
receives a Completer Abort completion packet. Software clears this
bit by writing a 1 to it.
11
RO
0b
Uncore
Signaled Target Abort Status (STAS)
The processor will not generate a Target Abort DMI completion
The processor will not generate a Target Abort DMI completion
packet or Special Cycle. This bit is not implemented and is
hardwired to a 0. Writes to this bit position have no effect.
10:9
RO
00b
Uncore
DEVSEL Timing (DEVT)
These bits are hardwired to "00". Writes to these bit positions have
These bits are hardwired to "00". Writes to these bit positions have
no effect. Device 0 does not physically connect to PCI_A. These
bits are set to "00" (fast decode) so that optimum DEVSEL timing
for PCI_A is not limited by the Host.