Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Processor Configuration Registers
78
Datasheet, Volume 2
2.5.30
G Memory Base Register
This register contains the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory
(PCI Device 0, Offset B4h, bits 31:20).
base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory
(PCI Device 0, Offset B4h, bits 31:20).
Note:
BIOS must program TSEGMB to a 8 MB naturally aligned boundary.
B/D/F/Type:
0/0/0/PCI
Address Offset:
B8–BBh
Reset Value:
0000_0000h
Access:
RW-KL, RW-L
Size:
32 bits
BIOS Optimal Default
00000h
Bit
Attr
Reset
Value
RST/
PWR
Description
31:20
RW-L
000h
Uncore
TESG Memory base (TSEGMB)
This register contains the base address of TSEG DRAM memory.
This register contains the base address of TSEG DRAM memory.
BIOS determines the base of TSEG memory which must be at or
below Graphics Base of GTT Stolen Memory (PCI Device 0, Offset
B4h, bits 31:20).
19:1
RO
0h
Reserved
0
RW-KL
0b
Uncore
Lock (LOCK)
This bit will lock all writeable settings in this register, including
This bit will lock all writeable settings in this register, including
itself.