Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
91
Processor Configuration Registers
2.6.7
CL1—Cache Line Size Register
2.6.8
HDR1—Header Type Register
This register identifies the header layout of the configuration space. No physical
register exists at this location.
register exists at this location.
2.6.9
PBUSN1—Primary Bus Number Register
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus 0.
bus 0.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
Ch
Reset Value:
00h
Access:
RW
Size:
8 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
7:0
RW
00h
Uncore
Cache Line Size (CLS)
Implemented by PCI Express devices as a read-write field for
Implemented by PCI Express devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI
Express device functionality.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
Eh
Reset Value:
81h
Access:
RO
Size:
8 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
7:0
RO
81h
Uncore
Header Type Register (HDR)
Device 1 returns 81h to indicate that this is a multi function device
Device 1 returns 81h to indicate that this is a multi function device
with bridge header layout.
Device 6 returns 01h to indicate that this is a single function device
Device 6 returns 01h to indicate that this is a single function device
with bridge header layout.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
18h
Reset Value:
00h
Access:
RO
Size:
8 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
7:0
RO
00h
Uncore
Primary Bus Number (BUSN)
Configuration software typically programs this field with the
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since the
processor root port is an internal device and its primary bus is
always 0, these bits are read only and are hardwired to 0.