Intel G640T CM8062301002204 User Manual

Datasheet, Volume 2

93

This register controls the processor to PCI Express-G I/O access routing based on the 
following formula: 

IO_BASE  address  IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode, address 
bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be 
aligned to a 4 KB boundary.

This register controls the processor to PCI Express-G I/O access routing based on the 
following formula: 

IO_BASE  address  IO_LIMIT 

Only upper 4 bits are programmable. For the purpose of address decode, address bits 
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be 
at the top of a 4 KB aligned address block.

7:4

RW

Fh

Uncore

I/O Address Base (IOBASE)
This field corresponds to A[15:12] of the I/O addresses passed by 

the root port to PCI Express-G.

3:0

RO

0h

7:4

RW

0h

Uncore

I/O Address Limit (IOLIMIT)
This field corresponds to A[15:12] of the I/O address limit of the 

root port. Devices between this upper limit and IOBASE1 will be 

passed to the PCI Express hierarchy associated with this device. 

3:0

RO

0h