Intel i5-2540M FF8062700839209 User Manual

Product codes
FF8062700839209
Page of 181
Features Summary
18
Datasheet
GPU
Graphics Processing Unit
ICH
The legacy I/O Controller Hub component that contains the main PCI 
interface, LPC interface, USB2, Serial ATA, and other I/O functions. It 
communicates with the legacy (G)MCH over a proprietary interconnect 
called DMI. 
IMC
Integrated Memory Controller
Intel® 64 Technology
64-bit memory extensions to the IA-32 architecture
Intel® FDI
Intel® Flexible Display Interface 
Intel® TXT
Intel® Trusted Execution Technology
Intel® VT-d
Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel 
VT-d is a hardware assist, under system software (Virtual Machine 
Manager or OS) control, for enabling I/O device virtualization. Intel 
VT-d also brings robust security by providing protection from errant 
DMAs by using DMA remapping, a key feature of Intel VT-d.
Intel® Virtualization 
Technology 
Processor virtualization which when used in conjunction with Virtual 
Machine Monitor software enables multiple, robust independent 
software environments inside a single platform.
ITPM
Integrated Trusted Platform Module
IOV
I/O Virtualization
LCD
Liquid Crystal Display
LVDS
Low Voltage Differential Signaling. A high speed, low power data 
transmission standard used for display connections to LCD panels.
MCP
Multi-Chip Package.
NCTF
Non-Critical to Function. NCTF locations are typically redundant 
ground or non-critical reserved, so the loss of the solder joint 
continuity at end of life conditions will not affect the overall product 
functionality.
PCH
Platform Controller Hub. The Intel chipset introduced in 2009 with 
centralized platform capabilities including the main I/O interfaces 
along with display connectivity, audio features, power management, 
manageability, security and storage features. The PCH may also be 
referred to using the name (Mobile) Intel® 5 Series Chipset
PECI
Platform Environment Control Interface.
PEG
PCI Express* Graphics. External Graphics using PCI Express 
Architecture. A high-speed serial interface whose configuration is 
software compatible with the existing PCI specifications. 
Processor
The 64-bit, single-core or multi-core component (package).
Processor Core
The term “processor core” refers to Si die itself which can contain 
multiple execution cores. Each execution core has an instruction 
cache, data cache, and 256-KB L2 cache. All execution cores share the 
L3 cache. 
Rank
A unit of DRAM corresponding four to eight devices in parallel, ignoring 
ECC. These devices are usually, but not always, mounted on a single 
side of a SO-DIMM.
SCI
System Control Interrupt. Used in ACPI protocol.
Term
Description