Intel i5-2540M FF8062700839209 User Manual

Product codes
FF8062700839209
Page of 181
Signal Description
78
Datasheet
6.11
Power Sequencing
Table 36.
Power Sequencing
Signal Name
Description 
Direction/Buffer 
Type
VCCPWRGOOD_0
VCCPWRGOOD_1
VCCPWRGOOD_0 and VCCPWRGOOD_1 
(Power Good) Processor Input:
 The 
processor requires these signals to be a 
clean indication that:
-VCC, VCCPLL, and VTT supplies are stable 
and within their specifications
-BCLK is stable and has been running for a 
minimum number of cycles.
Both signals must then transition 
monotonically to a high state. 
VCCPWRGOOD_0 and VCCPWRGOOD_1 can 
be driven inactive at any time, but BCLK and 
power must again be stable before a 
subsequent rising edge of these signals.  
VCCPWRGOOD_0 and VCCPWRGOOD_1 
should be tied together and connected to the 
PROCPWRGD output signal of the PCH.
I
Asynchronous CMOS
SM_DRAMPWROK
SM_DRAMPWROK Processor Input
Connects to PCH DRAMPWROK.
I
Asynchronous CMOS
VTTPWRGOOD
VTTPWRGOOD Processor Input: The 
processor requires this input signal to be a 
clean indication that the VTT power supply is 
stable and within specifications. Clean 
implies that the signal will remain low 
(capable of sinking leakage current), without 
glitches, from the time that the power 
supplies are turned on until they come within 
specification. The signal must then transition 
monotonically to a high state. Note it is not 
valid for VTTPWRGOOD to be deasserted 
while VCCPWRGOOD_0 and 
VCCPWRGOOD_1 is asserted.
I
Asynchronous CMOS
SKTOCC#(rPGA988A only)
PROC_DETECT (BGA only)
SKTOCC# (Socket Occupied)/
PROC_DETECT (Processor Detect):
 pulled 
to ground on the processor package. There is 
no connection to the processor silicon for this 
signal. System board designers may use this 
signal to determine if the processor is 
present.