Intel G550T CM8062301002309 User Manual

180

Datasheet, Volume 2

This register allows control of PCI Express Root Complex specific parameters. The 
system error control bits in this register determine if corresponding SERRs are 
generated when our device detects an error (reported in this device's Device Status 
register) or when an error message is received across the link. Reporting of SERR as 
controlled by these bits takes precedence over the SERR Enable in the PCI Command 
Register.

3

RW1C

0b

Uncore

Presence Detect Changed (PDC)
A pulse indication that the inband presence detect state has 

changed.
This bit is set when the value reported in Presence Detect State is 

changed.

2

RO

0b

Uncore

Reserved for MRL Sensor Changed (MSC)
If an MRL sensor is implemented, this bit is set when a MRL Sensor 

state change is detected. If an MRL sensor is not implemented, this 

bit must not be set.

1

RO

0b

Uncore

Reserved for Power Fault Detected (PFD)
If a Power Controller that supports power fault detection is 

implemented, this bit is set when the Power Controller detects a 

power fault at this slot. Note that, depending on hardware 

capability, it is possible that a power fault can be detected at any 

time, independent of the Power Controller Control setting or the 

occupancy of the slot. If power fault detection is not supported, 

this bit must not be set.

0

RO

0b

Uncore

Reserved for Attention Button Pressed (ABP)
If an Attention Button is implemented, this bit is set when the 

attention button is pressed. If an Attention Button is not 

supported, this bit must not be set.

15:3

RO

0h

2

RW

0b

Uncore

System Error on Fatal Error Enable (SEFEE)
Controls the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.

1 = Indicates that an SERR should be generated if a fatal error is 

reported by any of the devices in the hierarchy associated 

with this Root Port, or by the Root Port itself.

1:0

RO

0h