Intel G550T User Manuals

Table of Contents

• 1 Introduction

  11
• 2 Processor Configuration Registers

  13
  • 2.1 Register Terminology

    13
  • 2.2 PCI Devices and Functions on Processor

    14
  • 2.3 System Address Map

    15
    • 2.3.1 Legacy Address Range

      18
    • 2.3.2 Main Memory Address Range (1 MB – TOLUD)

      20
    • 2.3.3 PCI Memory Address Range (TOLUD – 4 GB)

      23
    • 2.3.4 Main Memory Address Space (4 GB to TOUUD)

      26
    • 2.3.5 PCI Express* Configuration Address Space

      32
    • 2.3.6 PCI Express* Graphics Attach (PEG)

      33
    • 2.3.7 Graphics Memory Address Ranges

      34
    • 2.3.8 System Management Mode (SMM)

      35
    • 2.3.9 SMM and VGA Access through GTT TLB

      35
    • 2.3.10 Intel® Management Engine (Intel ME) Stolen Memory Accesses

      35
    • 2.3.11 I/O Address Space

      36
    • 2.3.12 Management Component Transport Protocol (MCTP) and Kernel-based Virtual Machine (KVM) Flows

      37
    • 2.3.13 Decode Rules and Cross-Bridge Address Mapping

      37
  • 2.4 Processor Register Introduction

    45
    • 2.4.1 I/O Mapped Registers

      46
  • 2.5 PCI Device 0, Function 0 Configuration Registers

    46
    • 2.5.1 VID—Vendor Identification Register

      48
    • 2.5.2 DID—Device Identification Register

      48
    • 2.5.3 PCICMD—PCI Command Register

      49
    • 2.5.4 PCISTS—PCI Status Register

      50
    • 2.5.5 RID—Revision Identification Register

      52
    • 2.5.6 CC—Class Code Register

      53
    • 2.5.7 HDR—Header Type Register

      53
    • 2.5.8 SVID—Subsystem Vendor Identification Register

      54
    • 2.5.9 SID—Subsystem Identification Register

      54
    • 2.5.10 PXPEPBAR—PCI Express Egress Port Base Address Register

      55
    • 2.5.11 MCHBAR—Host Memory Mapped Register Range Base Register

      56
    • 2.5.12 GGC—GMCH Graphics Control Register Register

      57
    • 2.5.13 DEVEN—Device Enable Register

      59
    • 2.5.14 PCIEXBAR—PCI Express Register Range Base Address Register

      60
    • 2.5.15 DMIBAR—Root Complex Register Range Base Address Register

      62
    • 2.5.16 PAM0—Programmable Attribute Map 0 Register

      63
    • 2.5.17 PAM1—Programmable Attribute Map 1 Register

      64
    • 2.5.18 PAM2—Programmable Attribute Map 2 Register

      65
    • 2.5.19 PAM3—Programmable Attribute Map 3 Register

      66
    • 2.5.20 PAM4—Programmable Attribute Map 4 Register

      67
    • 2.5.21 PAM5—Programmable Attribute Map 5 Register

      68
    • 2.5.22 PAM6—Programmable Attribute Map 6 Register

      69
    • 2.5.23 LAC—Legacy Access Control Register

      70
    • 2.5.24 REMAPBASE—Remap Base Address Register

      74
    • 2.5.25 REMAPLIMIT—Remap Limit Address Register

      74
    • 2.5.26 TOM—Top of Memory Register

      75
    • 2.5.27 TOUUD—Top of Upper Usable DRAM Register

      76
    • 2.5.28 BDSM—Base Data of Stolen Memory Register

      77
    • 2.5.29 BGSM—Base of GTT stolen Memory Register

      77
    • 2.5.30 G Memory Base Register

      78
    • 2.5.31 TOLUD—Top of Low Usable DRAM Register

      79
    • 2.5.32 SKPD—Scratchpad Data Register

      80
    • 2.5.33 CAPID0_A—Capabilities A Register

      81
  • 2.6 PCI Device 1, Function 0–2 Configuration Registers

    83
    • 2.6.1 VID1—Vendor Identification Register

      85
    • 2.6.2 DID1—Device Identification Register

      85
    • 2.6.3 PCICMD1—PCI Command Register

      86
    • 2.6.4 PCISTS1—PCI Status Register

      88
    • 2.6.5 RID1—Revision Identification Register

      90
    • 2.6.6 CC1—Class Code Register

      90
    • 2.6.7 CL1—Cache Line Size Register

      91
    • 2.6.8 HDR1—Header Type Register

      91
    • 2.6.9 PBUSN1—Primary Bus Number Register

      91
    • 2.6.10 SBUSN1—Secondary Bus Number Register

      92
    • 2.6.11 SUBUSN1—Subordinate Bus Number Register

      92
    • 2.6.12 IOBASE1—I/O Base Address Register

      93
    • 2.6.13 IOLIMIT1—I/O Limit Address Register

      93
    • 2.6.14 SSTS1—Secondary Status Register

      94
    • 2.6.15 MBASE1—Memory Base Address Register

      95
    • 2.6.16 MLIMIT1—Memory Limit Address Register

      96
    • 2.6.17 PMBASE1—Prefetchable Memory Base Address Register

      97
    • 2.6.18 PMLIMIT1—Prefetchable Memory Limit Address Register

      98
    • 2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper Register

      99
    • 2.6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper Register

      100
    • 2.6.21 CAPPTR1—Capabilities Pointer Register

      100
    • 2.6.22 INTRLINE1—Interrupt Line Register

      101
    • 2.6.23 INTRPIN1—Interrupt Pin Register

      101
    • 2.6.24 BCTRL1—Bridge Control Register

      102
    • 2.6.25 PM_CAPID1—Power Management Capabilities Register

      104
    • 2.6.26 PM_CS1—Power Management Control/Status Register

      105
    • 2.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register

      106
    • 2.6.28 SS—Subsystem ID and Subsystem Vendor ID Register

      107
    • 2.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register

      107
    • 2.6.30 MC—Message Control Register

      108
    • 2.6.31 MA—Message Address Register

      109
    • 2.6.32 MD—Message Data Register

      109
    • 2.6.33 PEG_CAPL—PCI Express-G Capability List Register

      109
    • 2.6.34 PEG_CAP—PCI Express-G Capabilities Register

      110
    • 2.6.35 DCAP—Device Capabilities Register

      110
    • 2.6.36 DCTL—Device Control Register

      111
    • 2.6.37 DSTS—Device Status Register

      112
    • 2.6.38 LCTL—Link Control Register

      113
    • 2.6.39 LSTS—Link Status Register

      115
    • 2.6.40 SLOTCAP—Slot Capabilities Register

      116
    • 2.6.41 SLOTCTL—Slot Control Register

      118
    • 2.6.42 SLOTSTS—Slot Status Register

      120
    • 2.6.43 RCTL—Root Control Register

      122
    • 2.6.44 LCTL2—Link Control 2 Register

      123
  • 2.7 PCI Device 1, Function 0–2 Extended Configuration Registers

    125
    • 2.7.1 PVCCAP1—Port VC Capability Register 1

      125
    • 2.7.2 PVCCAP2—Port VC Capability Register 2

      126
    • 2.7.3 PVCCTL—Port VC Control Register

      126
    • 2.7.4 VC0RCAP—VC0 Resource Capability Register

      127
    • 2.7.5 VC0RCTL—VC0 Resource Control Register

      128
    • 2.7.6 VC0RSTS—VC0 Resource Status Register

      129
    • 2.7.7 PEG_TC—PCI Express Completion Time-out Register

      129
  • 2.8 PCI Device 2 Configuration Registers

    130
    • 2.8.1 VID2—Vendor Identification Register

      131
    • 2.8.2 DID2—Device Identification Register

      131
    • 2.8.3 PCICMD2—PCI Command Register

      132
    • 2.8.4 PCISTS2—PCI Status Register

      133
    • 2.8.5 RID2—Revision Identification Register

      134
    • 2.8.6 CC—Class Code Register

      134
    • 2.8.7 CLS—Cache Line Size Register

      135
    • 2.8.8 MTXT2—Master Latency Timer Register

      135
    • 2.8.9 HDR2—Header Type Register

      135
    • 2.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register

      136
    • 2.8.11 GMADR—Graphics Memory Range Address Register

      137
    • 2.8.12 IOBAR—I/O Base Address Register

      138
    • 2.8.13 SVID2—Subsystem Vendor Identification Register

      138
    • 2.8.14 SID2—Subsystem Identification Register

      139
    • 2.8.15 ROMADR—Video BIOS ROM Base Address Register

      139
    • 2.8.16 INTRPIN—Interrupt Pin Register

      139
    • 2.8.17 MINGNT—Minimum Grant Register

      140
    • 2.8.18 MAXLAT—Maximum Latency Register

      140
    • 2.8.19 MSAC—Multi Size Aperture Control Register

      141
  • 2.9 Device 2 I/O Registers

    142
    • 2.9.1 INDEX—MMIO Address Register

      142
    • 2.9.2 DATA—MMIO Data Register

      142
  • 2.10 PCI Device 6 Configuration Registers

    143
    • 2.10.1 VID6—Vendor Identification Register

      144
    • 2.10.2 DID6—Device Identification Register

      145
    • 2.10.3 PCICMD6—PCI Command Register

      145
    • 2.10.4 PCISTS6—PCI Status Register

      147
    • 2.10.5 RID6—Revision Identification Register

      149
    • 2.10.6 CC6—Class Code Register

      149
    • 2.10.7 CL6—Cache Line Size Register

      150
    • 2.10.8 HDR6—Header Type Register

      150
    • 2.10.9 PBUSN6—Primary Bus Number Register

      150
    • 2.10.10 SBUSN6—Secondary Bus Number Register

      151
    • 2.10.11 SUBUSN6—Subordinate Bus Number Register

      151
    • 2.10.12 IOBASE6—I/O Base Address Register

      152
    • 2.10.13 IOLIMIT6—I/O Limit Address Register

      152
    • 2.10.14 SSTS6—Secondary Status Register

      153
    • 2.10.15 MBASE6—Memory Base Address Register

      154
    • 2.10.16 MLIMIT6—Memory Limit Address Register

      155
    • 2.10.17 PMBASE6—Prefetchable Memory Base Address Register

      156
    • 2.10.18 PMLIMIT6—Prefetchable Memory Limit Address Register

      157
    • 2.10.19 PMBASEU6—Prefetchable Memory Base Address Upper Register

      158
    • 2.10.20 PMLIMITU6—Prefetchable Memory Limit Address Upper Register

      159
    • 2.10.21 CAPPTR6—Capabilities Pointer Register

      159
    • 2.10.22 INTRLINE6—Interrupt Line Register

      160
    • 2.10.23 INTRPIN6—Interrupt Pin Register

      160
    • 2.10.24 BCTRL6—Bridge Control Register

      161
    • 2.10.25 PM_CAPID6—Power Management Capabilities Register

      163
    • 2.10.26 PM_CS6—Power Management Control/Status Register

      164
    • 2.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register

      165
    • 2.10.28 SS—Subsystem ID and Subsystem Vendor ID Register

      166
    • 2.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register

      166
    • 2.10.30 MC—Message Control Register

      167
    • 2.10.31 MA—Message Address Register

      168
    • 2.10.32 MD—Message Data Register

      168
    • 2.10.33 PEG_CAPL—PCI Express-G Capability List Register

      168
    • 2.10.34 PEG_CAP—PCI Express-G Capabilities Register

      169
    • 2.10.35 DCAP—Device Capabilities Register

      169
    • 2.10.36 DCTL—Device Control Register

      170
    • 2.10.37 DSTS—Device Status Register

      171
    • 2.10.38 LCTL—Link Control Register

      172
    • 2.10.39 LSTS—Link Status Register

      174
    • 2.10.40 SLOTCAP—Slot Capabilities Register

      175
    • 2.10.41 SLOTCTL—Slot Control Register

      177
    • 2.10.42 SLOTSTS—Slot Status Register

      179
    • 2.10.43 RCTL—Root Control Register

      180
  • 2.11 PCI Device 6 Extended Configuration Registers

    181
    • 2.11.1 PVCCAP1—Port VC Capability Register 1

      181
    • 2.11.2 PVCCAP2—Port VC Capability Register 2

      182
    • 2.11.3 PVCCTL—Port VC Control Register

      182
    • 2.11.4 VC0RCAP—VC0 Resource Capability Register

      183
    • 2.11.5 VC0RCTL—VC0 Resource Control Register

      184
    • 2.11.6 VC0RSTS—VC0 Resource Status Register

      185
  • 2.12 DMIBAR Registers

    186
    • 2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Register

      187
    • 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1

      188
    • 2.12.3 DMIPVCCAP2—DMI Port VC Capability Register 2

      188
    • 2.12.4 DMIPVCCTL—DMI Port VC Control Register

      189
    • 2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register

      189
    • 2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register

      190
    • 2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register

      191
    • 2.12.8 DMIVC1RCAP—DMI VC1 Resource Capability Register

      191
    • 2.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register

      192
    • 2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register

      193
    • 2.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register

      193
    • 2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register

      194
    • 2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register

      195
    • 2.12.14 DMIESD—DMI Element Self Description Register

      196
    • 2.12.15 DMILE1D—DMI Link Entry 1 Description Register

      197
    • 2.12.16 DMILE1A—DMI Link Entry 1 Address Register

      197
    • 2.12.17 DMILE2D—DMI Link Entry 2 Description Register

      198
    • 2.12.18 DMILE2A—DMI Link Entry 2 Address Register

      198
    • 2.12.19 LCAP—Link Capabilities Register

      199
    • 2.12.20 LCTL—Link Control Register

      200
    • 2.12.21 LSTS—DMI Link Status Register

      201
    • 2.12.22 LCTL2—Link Control 2 Register

      202
    • 2.12.23 LSTS2—Link Status 2 Register

      204
    • 2.12.24 AFE_BMUF0—AFE BMU Configuration Function 0 Register

      204
    • 2.12.25 AFE_BMUT0—AFE BMU Configuration Test 0 Register

      204
  • 2.13 MCHBAR Registers in Memory Controller – Channel 0

    205
    • 2.13.1 TC_DBP_C0—Timing of DDR Bin Parameters Register

      205
    • 2.13.2 TC_RAP_C0—Timing of DDR Regular Access Parameters Register

      206
    • 2.13.3 SC_IO_LATENCY_C0—IO Latency Configuration Register

      206
    • 2.13.4 TC_SRFTP_C0—Self-Refresh Timing Parameters Register

      207
    • 2.13.5 PM_PDWN_config_C0—Power-down Configuration Register

      207
    • 2.13.6 TC_RFP_C0—Refresh Parameters Register

      208
    • 2.13.7 TC_RFTP_C0—Refresh Timing Parameters Register

      208
  • 2.14 MCHBAR Registers in Memory Controller – Channel 1

    209
    • 2.14.1 TC_DBP_C1—Timing of DDR Bin Parameters Register

      209
    • 2.14.2 TC_RAP_C1—Timing of DDR Regular Access Parameters Register

      210
    • 2.14.3 SC_IO_LATENCY_C1—IO Latency Configuration Register

      210
    • 2.14.4 TC_SRFTP_C1—Self-Refresh Timing Parameters Register

      211
    • 2.14.5 PM_PDWN_Config_C1—Power-down Configuration Register

      211
    • 2.14.6 TC_RFP_C1—Refresh Parameters Register

      212
    • 2.14.7 TC_RFTP_C1—Refresh Timing Parameters Register

      212
  • 2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH)

    213
    • 2.15.1 CRDTCTL3—Credit Control 3 Register

      213
  • 2.16 MCHBAR Registers in Memory Controller – Common

    214
    • 2.16.1 MAD_CHNL—Address Decoder Channel Configuration Register

      214
    • 2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register

      215
    • 2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register

      216
    • 2.16.4 PM_SREF_config—Self Refresh Configuration Register

      217
  • 2.17 Memory Controller MMIO Registers Broadcast Group

    218
    • 2.17.1 PM_PDWN_Config—Power-down Configuration Register

      218
    • 2.17.2 PM_CMD_PWR—Power Management Command Power Register

      219
    • 2.17.3 PM_BW_LIMIT_config—BW Limit Configuration Register

      219
  • 2.18 Integrated Graphics VT-d Remapping Engine Registers

    220
    • 2.18.1 VER_REG—Version Register

      221
    • 2.18.2 CAP_REG—Capability Register

      222
    • 2.18.3 ECAP_REG—Extended Capability Register

      225
    • 2.18.4 GCMD_REG—Global Command Register

      226
    • 2.18.5 GSTS_REG—Global Status Register

      230
    • 2.18.6 RTADDR_REG—Root-Entry Table Address Register

      231
    • 2.18.7 CCMD_REG—Context Command Register

      232
    • 2.18.8 FSTS_REG—Fault Status Register

      234
    • 2.18.9 FECTL_REG—Fault Event Control Register

      236
    • 2.18.10 FEDATA_REG—Fault Event Data Register

      237
    • 2.18.11 FEADDR_REG—Fault Event Address Register

      237
    • 2.18.12 FEUADDR_REG—Fault Event Upper Address Register

      237
    • 2.18.13 AFLOG_REG—Advanced Fault Log Register

      238
    • 2.18.14 PMEN_REG—Protected Memory Enable Register

      239
    • 2.18.15 PLMBASE_REG—Protected Low-Memory Base Register

      240
    • 2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register

      241
    • 2.18.17 PHMBASE_REG—Protected High-Memory Base Register

      242
    • 2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register

      243
    • 2.18.19 IQH_REG—Invalidation Queue Head Register

      244
    • 2.18.20 IQT_REG—Invalidation Queue Tail Register

      244
    • 2.18.21 IQA_REG—Invalidation Queue Address Register

      245
    • 2.18.22 ICS_REG—Invalidation Completion Status Register

      245
    • 2.18.23 IECTL_REG—Invalidation Event Control Register

      246
    • 2.18.24 IEDATA_REG—Invalidation Event Data Register

      247
    • 2.18.25 IEUADDR_REG—Invalidation Event Upper Address Register

      247
    • 2.18.26 IRTA_REG—Interrupt Remapping Table Address Register

      248
    • 2.18.27 IVA_REG—Invalidate Address Register

      249
    • 2.18.28 IOTLB_REG—IOTLB Invalidate Register

      250
    • 2.18.29 FRCDL_REG—Fault Recording Low Register

      252
    • 2.18.30 FRCDH_REG—Fault Recording High Register

      253
    • 2.18.31 VTPOLICY—DMA Remap Engine Policy Control Register

      254
  • 2.19 PCU MCHBAR Registers

    255
    • 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register

      256
    • 2.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register

      257
    • 2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register

      258
    • 2.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register

      259
    • 2.19.5 MEM_TRML_INTERRUPT—Memory Thermal Interrupt Register

      259
    • 2.19.6 GT_PERF_STATUS—GT Performance Status Register

      260
    • 2.19.7 RP_STATE_CAP—RP State Capability Register

      260
    • 2.19.8 SSKPD—Sticky Scratchpad Data Register

      261
  • 2.20 PXPEPBAR Registers

    263
    • 2.20.1 EPVC0RCTL—EP VC 0 Resource Control Register

      263
  • 2.21 Default PEG/DMI VT-d Remapping Engine Registers

    264
    • 2.21.1 VER_REG—Version Register

      265
    • 2.21.2 CAP_REG—Capability Register

      266
    • 2.21.3 ECAP_REG—Extended Capability Register

      269
    • 2.21.4 GCMD_REG—Global Command Register

      270
    • 2.21.5 GSTS_REG—Global Status Register

      274
    • 2.21.6 RTADDR_REG—Root-Entry Table Address Register

      275
    • 2.21.7 CCMD_REG—Context Command Register

      276
    • 2.21.8 FSTS_REG—Fault Status Register

      278
    • 2.21.9 FECTL_REG—Fault Event Control Register

      280
    • 2.21.10 FEDATA_REG—Fault Event Data Register

      281
    • 2.21.11 FEADDR_REG—Fault Event Address Register

      281
    • 2.21.12 FEUADDR_REG—Fault Event Upper Address Register

      281
    • 2.21.13 AFLOG_REG—Advanced Fault Log Register

      282
    • 2.21.14 PMEN_REG—Protected Memory Enable Register

      283
    • 2.21.15 PLMBASE_REG—Protected Low-Memory Base Register

      284
    • 2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register

      285
    • 2.21.17 PHMBASE_REG—Protected High-Memory Base Register

      286
    • 2.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register

      287
    • 2.21.19 IQH_REG—Invalidation Queue Head Register

      288
    • 2.21.20 EG—Invalidation Queue Tail Register

      288
    • 2.21.21 IQA_REG—Invalidation Queue Address Register

      289
    • 2.21.22 ICS_REG—Invalidation Completion Status Register

      289
    • 2.21.23 IECTL_REG—Invalidation Event Control Register

      290
    • 2.21.24 IEDATA_REG—Invalidation Event Data Register

      291
    • 2.21.25 IEADDR_REG—Invalidation Event Address Register

      291
    • 2.21.26 IEUADDR_REG—Invalidation Event Upper Address Register

      292
    • 2.21.27 IRTA_REG—Interrupt Remapping Table Address Register

      292
    • 2.21.28 IVA_REG—Invalidate Address Register

      293
    • 2.21.29 IOTLB_REG—IOTLB Invalidate Register

      294