Intel G550T CM8062301002309 User Manual
Product codes
CM8062301002309
Datasheet, Volume 2
25
Processor Configuration Registers
2.3.3.1
APIC Configuration Space (FEC0_0000h–FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the PCH portion of the chip-set, but may also exist as stand-alone components like
PXH.
the PCH portion of the chip-set, but may also exist as stand-alone components like
PXH.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The processor optionally supports additional I/O APICs behind the PCI Express
“Graphics” port. When enabled using the APIC_BASE and APIC_LIMIT registers
(mapped PCI Express Configuration space offset 240h and 244h), the PCI Express
port(s) will positively decode a subset of the APIC configuration space.
“Graphics” port. When enabled using the APIC_BASE and APIC_LIMIT registers
(mapped PCI Express Configuration space offset 240h and 244h), the PCI Express
port(s) will positively decode a subset of the APIC configuration space.
Memory requests to this range would then be forwarded to the PCI Express port. This
mode is intended for the entry Workstation/Server SKUs of the processor, and would be
disabled in typical Desktop systems. When disabled, any access within entire APIC
Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
mode is intended for the entry Workstation/Server SKUs of the processor, and would be
disabled in typical Desktop systems. When disabled, any access within entire APIC
Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
2.3.3.2
HSEG (FEDA_0000h–FEDB_FFFFh)
This decode range is not supported on the processor platform.
2.3.3.3
MSI Interrupt Memory Space (FEE0_0000h–FEEF_FFFFh)
Any PCI Express or DMI device may issue a Memory Write to 0FEEx_xxxxh. This
Memory Write cycle does not go to DRAM. The system agent will forward this Memory
Write along with the data to the processor as an Interrupt Message Transaction.
Memory Write cycle does not go to DRAM. The system agent will forward this Memory
Write along with the data to the processor as an Interrupt Message Transaction.
2.3.3.4
High BIOS Area
For security reasons, the processor will positively decode this range to DMI. This
positive decode will ensure any overlapping ranges will be ignored.
positive decode will ensure any overlapping ranges will be ignored.
The top 2 MB (FFE0_0000h–FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The processor begins execution from the High BIOS after reset. This
region is positively decoded to DMI. The actual address space required for the BIOS is
less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that
full 2 MB must be considered.
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The processor begins execution from the High BIOS after reset. This
region is positively decoded to DMI. The actual address space required for the BIOS is
less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that
full 2 MB must be considered.