Intel G550T CM8062301002309 User Manual
Product codes
CM8062301002309
Processor Configuration Registers
42
Datasheet, Volume 2
Accesses to the VGA memory range are directed to IGD depend on the configuration.
The configuration is specified by:
The configuration is specified by:
• Internal Graphics Controller in Device 2 is enabled (DEVEN.D2EN bit 4)
• Internal Graphics VGA in Device 0, function 0 is enabled through register GGC bit 1.
• IGD memory accesses (PCICMD2 04 – 05h, MAE bit 1) in Device 2 configuration
• Internal Graphics VGA in Device 0, function 0 is enabled through register GGC bit 1.
• IGD memory accesses (PCICMD2 04 – 05h, MAE bit 1) in Device 2 configuration
space are enabled.
• VGA Compatibility Memory accesses (VGA Miscellaneous output Register - MSR
Register, bit 1) are enabled.
• Software sets the proper value for VGA Memory Map Mode Register (VGA GR06
for translations.
Note:
Additional qualification within IGD comprehends internal MDA support. The VGA and
MDA enabling bits detailed below control segments not mapped to IGD.
VGA I/O range is defined as addresses where A[15:0] are in the ranges 03B0h to
03BBh, and 03C0h to 03DFh. VGA I/O accesses are directed to IGD depends on the
following configuration.
03BBh, and 03C0h to 03DFh. VGA I/O accesses are directed to IGD depends on the
following configuration.
• Internal Graphics Controller in Device 2 is enabled through register DEVEN.D2EN
bit 4.
• Internal Graphics VGA in Device 0 function 0 is enabled through register GGC bit 1.
• IGD I/O accesses (PCICMD2 04 – 05h, IOAE bit 0) in Device 2 are enabled.
• VGA I/O decodes for IGD uses 16 address bits (15:0) there is no aliasing. Note that
• IGD I/O accesses (PCICMD2 04 – 05h, IOAE bit 0) in Device 2 are enabled.
• VGA I/O decodes for IGD uses 16 address bits (15:0) there is no aliasing. Note that
this is different when compared to a bridge device (Device 1) that used only 10
address bits (A 9:0) for VGA I/O decode.
address bits (A 9:0) for VGA I/O decode.
• VGA I/O input/output address select (VGA Miscellaneous output Register – MSR
Register, bit 0) used to select mapping of I/O access as defined in
.
Note:
Additional qualification within IGD comprehends internal MDA support. The VGA and
MDA enabling bits detailed below control ranges not mapped to IGD.
Table 2-4.
IGD Frame Buffer Accesses
Mem Access
GR06(3:2)
A0000h–AFFFFh
B0000h–B7FFFh
MDA
B8000h–BFFFFh
00
IGD
IGD
IGD
01
IGD
PCI Express Bridge or DMI
Interface
PCI Express Bridge or DMI
Interface
10
PCI Express Bridge or
DMI Interface
IGD
PCI Express Bridge or DMI
Interface
11
PCI Express Bridge or
DMI Interface
PCI Express Bridge or DMI
Interface
IGD
Table 2-5.
IGD VGA I/O Mapping
I/O Access
MSRb0
3CX
3DX
3B0–3BB
3BC–3BF
0
IGD
PCI Express Bridge or DMI
Interface
IGD
PCI Express Bridge or
DMI Interface
1
IGD
IGD
PCI Express Bridge or
DMI Interface
PCI Express Bridge or
DMI Interface