Intel G645 CM8062301262601 User Manual
Product codes
CM8062301262601
Processor Configuration Registers
26
Datasheet, Volume 2
2.3.4
Main Memory Address Space (4 GB to TOUUD)
The processor supports 39-bit addressing.
The maximum main memory size supported is 32 GB total DRAM memory. A hole
between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger.
As a result, TOM, and TOUUD registers and REMAPBASE/REMAPLIMIT registers become
relevant.
between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger.
As a result, TOM, and TOUUD registers and REMAPBASE/REMAPLIMIT registers become
relevant.
The remap configuration registers exist to remap lost main memory space. The greater
than 32-bit remap handling will be handled similar to other MCHs.
than 32-bit remap handling will be handled similar to other MCHs.
Upstream read and write accesses above 39-bit addressing are treated as invalid cycles
by PEG and DMI.
by PEG and DMI.
Top of Memory (TOM)
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory mapped IO above
TOM).
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory mapped IO above
TOM).
On FSB chipsets, the TOM was used to allocate the Intel ME's stolen memory. The Intel
ME's stolen size register reflects the total amount of physical memory stolen by the
Management Engine. The Intel ME stolen memory is located at the top of physical
memory. The Intel ME stolen memory base is calculated by subtracting the amount of
memory stolen by the Management Engine from TOM.
ME's stolen size register reflects the total amount of physical memory stolen by the
Management Engine. The Intel ME stolen memory is located at the top of physical
memory. The Intel ME stolen memory base is calculated by subtracting the amount of
memory stolen by the Management Engine from TOM.
Top of Upper Usable DRAM (TOUUD)
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of
addressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Intel ME's
stolen size. If remap is enabled, then it will reflect the remap limit. Note, when there is
more than 4 GB of DRAM and reclaim is enabled, the reclaim base will be the same as
TOM minus Intel ME stolen memory size to the nearest 1 MB alignment (shown in case
2 below).
addressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Intel ME's
stolen size. If remap is enabled, then it will reflect the remap limit. Note, when there is
more than 4 GB of DRAM and reclaim is enabled, the reclaim base will be the same as
TOM minus Intel ME stolen memory size to the nearest 1 MB alignment (shown in case
2 below).
Top of Low Usable DRAM (TOLUD)
TOLUD register is restricted to 4 GB memory (A[31:20]), but the processor can support
up to 32 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range between the 4 GB boundary and the top of
physical memory. This identifies memory that can be directly accessed (including
remap address calculation), which is useful for memory access indication and early
path indication. TOLUD can be 1 MB aligned.
up to 32 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range between the 4 GB boundary and the top of
physical memory. This identifies memory that can be directly accessed (including
remap address calculation), which is useful for memory access indication and early
path indication. TOLUD can be 1 MB aligned.
TSEG_BASE
The “TSEG_BASE” register reflects the total amount of low addressable DRAM, below
TOLUD. BIOS will calculate and program this register, so the system agent has
knowledge of where (TOLUD)–(GFX stolen)–(GFX GTT stolen)–(TSEG) is located. I/O
blocks use this minus DPR for upstream DRAM decode.
TOLUD. BIOS will calculate and program this register, so the system agent has
knowledge of where (TOLUD)–(GFX stolen)–(GFX GTT stolen)–(TSEG) is located. I/O
blocks use this minus DPR for upstream DRAM decode.