Intel G645 CM8062301262601 User Manual

Datasheet, Volume 2

27

The following are examples of Memory Mapped IO devices that are typically located 
below 4 GB:

• High  BIOS 
• TSEG
• GFX  stolen
• GTT  stolen 
• XAPIC
• Local  APIC
• MSI Interrupts
• Mbase/Mlimit
• Pmbase/PMlimit
• Memory Mapped IO space that supports only 32B addressing

The processor provides the capability to re-claim the physical memory overlapped by 
the Memory Mapped IO logical address space. The processor re-maps physical memory 
from the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an 
equivalent sized logical address range located just below the Intel ME's stolen memory. 

This access is similar to prior chipsets, MCHBAR registers can be indirectly accessed 
using:

• Direct MCHBAR access decode

1. Cycle to memory from processor
2.

Hits MCHBAR base, AND

3.

MCHBAR is enabled, AND

4.

Within MMIO space (above and below 4 GB)

• GTTMMADR (10000h–13FFFh) range -> MCHBAR decode

1.

Cycle to memory from processor, AND

2.

Device 2 (IGD) is enabled, AND

3.

Memory accesses for device 2 is enabled, AND

4.

Targets GFX MMIO Function 0, AND

5.

MCHBAR is enabled or cycle is a read. If MCHBAR is disabled, only read 

access is allowed.

• MCHTMBAR  ->  MCHBAR

 (Thermal Monitor) 

1.

Cycle to memory from processor, AND

2.

AND Targets MCHTMBAR base

• IOBAR -> GTTMMADR -> MCHBAR.

Follows IOBAR rules. See GTTMMADR information above as well.