Supermicro Xeon P4X4-028-512K User Manual
Product codes
P4X4-028-512K
Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz
27
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50V.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50V.
2.12
AGTL+ Front Side Bus Specifications
Routing topologies are dependent on the number of processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines.
In most cases, termination
resistors are not required as these are integrated into the processor. See
Table 4
for details on which
AGTL+ signals do not include on-die termination.The termination resistors are enabled or disabled
through the ODTEN pin. To enable termination, this pin should be pulled up to V
CC
through a
resistor and to disable termination, this pin should be pulled down to V
SS
through a resistor. For
optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should
have a resistance value within 20 percent of the impedance of the baseboard transmission line
traces. For example, if the trace impedance is 50
Ω
, then a value between 40 and 60
Ω
should be
used
.
The processor's on-die termination must be enabled for the end agent only. Please refer to
Table 12
for termination resistor values. For more details on platform design see the appropriate
platform design guidelines.
Valid high and low levels are determined by the input buffers via comparing with a reference
voltage called GTLREF.
voltage called GTLREF.
Table 12
lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the baseboard using high precision voltage divider circuits. It is important that the
baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for
the AGTL+ signal group traces is known and well-controlled. For more details on platform design
the AGTL+ signal group traces is known and well-controlled. For more details on platform design
see the appropriate platform design guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable system designer to calculate the
2. The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of V
CC
.
3. GTLREF is generated from V
CC
on the baseboard by a voltage divider of 1 percent resistors. Refer to the
appropriate platform design guidelines for implementation details.
4. R
TT
is the on-die termination resistance measured from V
CC
to 1/3 V
CC
at the AGTL+ output driver. Refer to
the Intel
®
Xeon™ Processor with 533MHz Front Side Bus Signal Integrity Models for I/V characteristics.
5. COMP resistors are pull downs to V
SS
provided on the baseboard with 1% tolerance. See the appropriate
platform design guidelines for implementation details.
6. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
7. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the
recommended COMP resistance value.
Table 12. AGTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
GTLREF
Bus Reference Voltage
2/3 * V
CC
- 2%
2/3 * V
CC
2/3 * V
CC
+ 2%
V
2, 3, 6
GTLREF
New Design
Bus Reference Voltage
0.63*V
CC
- 2%
0.63*V
CC
0.63*V
CC
+
2%
V
2, 3, 6,
R
TT
Termination Resistance
36
41
46
Ω
4
R
TT
New
Design
Termination Resistance
45
50
55
Ω
4, 9
COMP[1:0]
COMP Resistance
42.77
43.2
43.63
Ω
5, 8
COMP[1:0]
New
Design
New
Design
COMP Resistance
49.55
50
50.45
Ω
5, 8, 9