NEC Intel Xeon E5-2420 N8101-571F User Manual

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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

Datasheet Volume One

• CKE Power-Down: Opportunistic, per rank control after idle time. There may be 

different levels.

— Active  Power-Down.
— Precharge Power-Down with Fast Exit.
— Precharge power Down with Slow Exit.

• Self Refresh: In this mode no transaction is executed. The DDR consumes the 

minimum possible power.

The CKE input land is used to enter and exit different power-down modes. The memory 

controller has a configurable activity timeout for each rank. Whenever no reads are 
present to a given rank for the configured interval, the memory controller will transition 

the rank to power-down mode.

The memory controller transitions the DRAM to power-down by de-asserting CKE and 
driving a NOP command. The memory controller will tri-state all DDR interface lands 

except CKE (de-asserted) and ODT while in power-down. The memory controller will 

transition the DRAM out of power-down state by synchronously asserting CKE and 
driving a NOP command.

When CKE is off the internal DDR clock is disabled and the DDR power is significantly 

reduced.

The DDR defines three levels of power-down:

• Active power-down.
• Precharge power-down fast exit.
• Precharge power-down slow exit.

The Power Control Unit (PCU) may request the memory controller to place the DRAMs 

in self refresh state. Self refresh per channel is supported. The BIOS can put the 
channel in self-refresh if software remaps memory to use a subset of all channels. Also 

processor channels can enter self refresh autonomously without PCU instruction when 

the package is in a package C0 state.

Self refresh entrance can be either disabled or triggered by an idle counter. The idle 

counter always clears with any access to the memory controller and remains clear as 
long as the memory controller is not drained. As soon as the memory controller is 

drained, the counter starts counting, and when it reaches the idle-count, the memory 

controller will place the DRAMs in self refresh state.

Power may be removed from the memory controller core at this point. But V

CCD

 supply 

(1.5 V or 1.35 V) to the DDR IO must be maintained.

Self refresh exit can be either a message from an external unit or as reaction for an 

incoming transaction.