Supermicro XEON 2.8GHz P4X-0028-2M-800L User Manual
Product codes
P4X-0028-2M-800L
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
29
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. V
9. V
Havg
can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.
10.
∆
V
CROSS
is defined as the total variation of all crossing voltages as defined in note 2.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. V
2. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
3. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4. V
IH
and V
ON
may experience excursions above V
CC
. However, input signal drivers must comply with the
signal quality specifications in
Chapter 3.0
.
5. Refer to the Intel
®
Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
6. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
7. V
OL_MAX
of 0.450 V is guaranteed when driving into a test load as indicated in
TT
enabled.
8. Leakage to V
CC
with pin held at 300 mV.
9. Leakage to V
SS
with pin held at V
CC
.
Table 9. TAP and PWRGOOD Signal Group DC Specifications
NOTES:.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
2. All outputs are open drain
Table 8. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1,7
V
IH
Input High Voltage
1.10 * GTLREF
V
CC
V
2, 4, 6
V
IL
Input Low Voltage
0.0
0.90 * GTLREF
V
3, 6
V
OH
Output High Voltage
N/A
V
CC
V
4, 6
I
OL
Output Low Current
N/A
V
CC
/
(0.50 * R
TT_min
+ R
ON_min
)
= 50
mA
6
I
HI
Pin Leakage High
N/A
100
µA
9
I
LO
Pin Leakage Low
N/A
500
µA
8
R
ON
Buffer On Resistance
7
11
Ω
5, 7
Symbol
Parameter
Min
Max
Unit
Notes
1, 2
V
HYS
TAP Input Hysteresis
200
300
8
V
T+
TAP input low to high
threshold voltage
0.5 * (V
CC
+ V
HYS_MIN
)
0.5 * (V
CC
+ V
HYS_MAX
)
5
V
T-
TAP input high to low
threshold voltage
0.5 * (V
CC
- V
HYS_MAX
)
0.5 * (V
CC
- V
HYS_MIN
)
5
V
OH
Output High Voltage
N/A
V
CC
V
3, 5
I
OL
Output Low Current
40
mA
6, 7
I
HI
Pin Leakage High
N/A
100
µA
10
I
LO
Pin Leakage Low
N/A
500
µA
9
R
ON
Buffer On Resistance
8.75
13.75
Ω
4