Intermec 074787-001 User Manual

MODCK [1:2] (not shown) are set to 00 on reset. The filter on VDDSYN 
provides a clean supply to the internal PLL. CLKOUT is connected to the 
SDRAM. EXTCLK is not used. R103 is not placed. 

To set the frequency of the system clock to 66 MHz make the following 
settings to PLPRCR: PDF = 0, MFI = 13, MFN = 2, MFD = 9, S = 1, 
DBRMO = 0. 

For SCCR: 

• COM = 00 (CLKOUT enabled) 

• TBS = 1 (Timebase is GCLK2/16) 

• PTDIV = 0 (PIT divider = 4) 

• PTSEL = 0 (Crystal oscillator selected)

• CRQEN = 0 (Remain in low frequency when CP is active)

• EBDF = 00 (CLKOUT = GCLK2)

• DFSYNC = 00 (Divide by 1)

• DFBRG = 00 (Divide by 1)

• DFNL = 111 (Divide by 256)

• DFNH = 000 (No division for high frequency mode)

• DFUTP, DFAUTP – Leave at default values. UTOPIA not used.

When HRESET* is asserted, U7 drives data bus pin 4. All of the others are 
internally pulled low. This process corresponds to these settings:

• Internal bus arbitration

• MSR[IP] = 0

• Boot device bursting disabled

• Memory controller activated

• 16-bit port size

• Internal space base address = 0x00000000

• Debug pin configuration = 00

• Debug port pin configuration = 00

• CLKOUT is GCLK2 divided by 1

• Big endian