Intermec 074787-001 User Manual

CS0 is the chip select line for the flash. The flash is accessed through one of 
the general-purpose chip-select machines (GPCM) of U1.

BR0 and OR0 configure the GPCM control of the flash. Below are the 
required settings for those two registers. All other settings can be selected at 
the firmware designer’s discretion.

BR0 = 0xXXXXX801:

• BA = Determined by firmware designer (Base address)

• AT = 000 (No address type masking)

• PS = 10 (16-bit port size)

• WP = 0 (Read and write allowed)

• MS = 00 (GPCM selected)

• V = 1 (Valid bank)

OR0 = 0xFFC00940:

• AM = 0xFFC00 (4 MB)

• ATM = 000 (No address type mask)

• CSNT = 1 (Chip-select negation time)

• ACS = 00 (CS* is output at the same time as the address)

• BIH = 1 (Bursting not supported)

• SCY = Number of wait states:

• 0101 for 73.17 MHz < system clock < 85.37 MHz

• 0100 for 60.98 MHz < system clock < 73.17 MHz