Intermec 074787-001 User Manual

0x0FFFFC34, 0x0FFFFC34, 0x0FFFFC34, 0x0FFFFC34, 
0x0FFFFC34, 0x1FFFFC35

• Exception: Addresses 0x3C – 0x3D = 0x0FF77C04, 0x1FFFFC05

• Initialization step #1: Addresses 0x2C – 0x2D = 0x0FF77C34, 

0x0FFFFC35

• Initialization step #2 and 3: Addresses 0x2E – 0x2F = 0x00F03C34, 

0x0FFFFC35

• Enter self refresh mode: Addresses 0x29 – 0x2B = 0x0FF77C34, 

0x0FFFFC34, 0x1FF5F035

• Exit self refresh mode: Addresses 0x10 – 0x15 = 0x0FFFFC34, 

0x0FFFFC34, 0x0FFFFC34, 0x0FFFFC34, 0x0FFFFC34, 
0x1FFFFC35

The SDRAM mode register is programmed as 0x0023. This corresponds to 
the following settings:

• Burst length = 8

• Burst type = Sequential

• CAS latency = 2

• Write burst mode = Programmed burst length

The SDRAM extended mode register is programmed as 0x2000. This 
corresponds to the following settings:

• Maximum case temperature for temperature compensated self refresh = 

70°C

• Self refresh coverage = All four banks

SDRAM initialization should be performed using the following steps:

Write patterns to the UPM RAM array.

Program MPTPR.

Program MBMR.

Program BR1.

Program OR1, except clear OR1[V].

Initialize the SDRAM and its registers.

Set OR1[V].

To load each word into the UPM RAM do the following:

Write the word contents to MDR.

Write 0x008021XX to MCR, where XX corresponds to the array 
address.