Intermec 074787-001 User Manual
Chapter 2 — Theory of Operation
PB42 Portable Receipt Printer Service Manual
13
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is used to communicate with five
external chips: the FRAM, input shift register, output shift register, DAC,
and ADC. The following sections describe the SPI settings and data format
for each of these slave devices. For more specific information on operation
of the MPC875 or any of the other SPI devices, see their respective
specifications.
external chips: the FRAM, input shift register, output shift register, DAC,
and ADC. The following sections describe the SPI settings and data format
for each of these slave devices. For more specific information on operation
of the MPC875 or any of the other SPI devices, see their respective
specifications.
FRAM
The FRAM is a fast, serial, non-volatile memory that can be used to store
critical printer or communications settings. It can store error codes, service
history, and so on. Since it is fast and non-volatile, the processor can use it
to store critical data when it knows that a power cut is imminent. (IRQ0 –
low battery) It is organized as 512 x 8 bits.
critical printer or communications settings. It can store error codes, service
history, and so on. Since it is fast and non-volatile, the processor can use it
to store critical data when it knows that a power cut is imminent. (IRQ0 –
low battery) It is organized as 512 x 8 bits.
The maximum data rate for the SPI interface is 20 MHz. SPMODE bits CI
and CP must be either 0, 0 or 1, 1. The MSB is always first, so
SPMODE[REV] is 1.
and CP must be either 0, 0 or 1, 1. The MSB is always first, so
SPMODE[REV] is 1.
The WP* and HOLD* pins of the FRAM are tied high. So the hold and
hardware write protect functions are disabled. Block memory protection
can be used, though, to write protect the upper quarter, half, or all of the
memory array. This is controlled through the status register.
hardware write protect functions are disabled. Block memory protection
can be used, though, to write protect the upper quarter, half, or all of the
memory array. This is controlled through the status register.
Data transfers with the FRAM can be any 8-bit multiple, depending on the
op-code being used and the amount of data to transfer. The maximum
buffer length for the MPC875 is only 16 bits per transfer. So, the processor
will have to span some transfers over several “chunks” when transferring
more than 16 bits to/from the FRAM. The FRAM_CS* pin (PA0) must
remain asserted over the entire transfer or the operation will be aborted.
op-code being used and the amount of data to transfer. The maximum
buffer length for the MPC875 is only 16 bits per transfer. So, the processor
will have to span some transfers over several “chunks” when transferring
more than 16 bits to/from the FRAM. The FRAM_CS* pin (PA0) must
remain asserted over the entire transfer or the operation will be aborted.
The “A” bit for the read and write op-codes are the MSB of the 9-bit
address.
address.
The FRAM always powers up with writes disabled. To enable writes to the
status register or the memory array, issue the WREN command once.
status register or the memory array, issue the WREN command once.
Memory Op-Codes
Name
Description
Op-Code
WREN
Set write enable latch
00000110b
WRDI
Write disable
00000100b
RDSR
Read status register
00000101b
WRSR
Write status register
00000001b
READ
Read memory data
0000A011b
WRITE
Write memory data
0000A010b