Intel 430 LF80538NE0301M Data Sheet

Product codes
LF80538NE0301M
Page of 69
14
Intel
®
 Celeron
®
 M Processor Datasheet
Low Power Features
BPRI# control for address and control input buffers
Dynamic on-die termination disabling
Low VCCP (I/O termination voltage)
The Intel Celeron M processor incorporates the DPWR# signal that controls the data bus input 
buffers on the processor. The DPWR# signal disables the buffers when not used and activates 
them only when data bus activity occurs, resulting in significant power savings with no 
performance impact. BPRI# control also allows the processor address and control input buffers to 
be turned off when the BPRI# signal is inactive. The On-Die termination on the processor FSB 
buffers is disabled when the signals are driven low, resulting in additional power savings. The low 
I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling 
low I/O switching power at all times. 
2.3
Processor Power Status Indicator (PSI#) Signal
The Intel Celeron M processor incorporates the PSI# signal that is asserted when the processor is in 
a low power (Deep Sleep ) state. This signal is asserted upon Deep Sleep entry and deasserted upon 
exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in 
platform power savings and extended battery life.