Intel 430 LF80538NE0301M Data Sheet

15

The Intel

 

Celeron M processor FSB uses Advanced Gunning Transceiver Logic (AGTL+) 

signalling technology, a variant of GTL+ signalling technology with low power enhancements. 

This signalling technology provides improved noise margins and reduced ringing through low-

voltage swings and controlled edge rates. The termination voltage level for the Intel Celeron M 
processor AGTL+ signals is VCCP

 

= 1.05 V (nominal). Due to speed improvements to data and 

address bus, signal integrity and platform design methods have become more critical than with 

previous processor families. Design guidelines for the Intel Celeron M processor FSB will be 
detailed in the platform design guides.

The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine 

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. 

Termination resistors are provided on the processor silicon and are terminated to its I/O voltage 
(VCCP). Intel’s 855PM, 855GM, and 852GM chipsets will also provide on-die termination, thus 

eliminating the need to terminate the bus on the system board for most AGTL+ signals. 

Refer to the platform design guides for board level termination resistor requirements.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ 

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the 
FSB, including trace lengths, is highly recommended when designing a system.

For clean on-chip power distribution, the Intel Celeron M processor will have a large number of 

V

CC

 (power) and V

SS 

(ground) inputs. All power pins must be connected to V

CC 

power planes while 

all V

SS

 pins must be connected to system ground planes. Use of multiple power and ground planes 

is recommended to reduce I 

x

 R drop. Please refer to the platform design guides for more details. 

The processor V

CC

 pins must be supplied the voltage determined by the VID (Voltage ID) pins. 

Due to its large number of transistors and high internal clock speeds, the processor is capable of 
generating large average current swings between low- and full-power states. This may cause 

voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. 

Care must be taken in the board design to ensure that the voltage provided to the processor remains 
within the specifications listed in 

. Failure to do so can result in timing violations or 

reduced lifetime of the component. For further information and design guidelines, refer to the 

platform design guides.