Intel 1005M AW8063801121200 User Manual

84

Datasheet, Volume 1

The integrated memory controller (IMC) provides thermal protection for system 
memory DIMMs using memory bandwidth throttling. Like processor package throttling, 
memory throttling is initiated based on temperature. The IMC offers two levels of 
throttling (warm and hot). The temperature and the amount of bandwidth reduced 
while throttling is programmable for the warm and hot trip points through memory 
mapped I/O registers.

Memory temperature can be read directly by a physical thermal sensor on the DIMM 
(TS-on-DIMM) or a physical temperature sensor placed on the motherboard (TS-on-
Board). Memory throttling based on physical temperature sensor readings is known as 
Closed Loop Thermal Throttling (CLTT). The memory temperature readings are 
reported from the platform to the memory controller using PECI.

If no physical thermal sensor is available, the memory controller can estimate the 
temperature based on memory activity. Memory thermal throttling that is initiated with 
no direct temperature reading is known as Open Loop Thermal Throttling (OLTT). The 
processor features the Virtual Temperature Sensor (VTS) for OLTT. 

The Platform Environment Control Interface (PECI) is a one-wire interface that provides 
a communication channel between Intel processor and chipset components to external 
monitoring devices. The processor implements a PECI interface to allow communication 
of processor thermal information to other devices on the platform. The processor 
provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at 
the factory to provide a digital representation of relative processor temperature. 
Averaged DTS values are read using the PECI interface.

The PECI physical layer is a self-clocked one-wire bus that begins each bit with a 
driven, rising edge from an idle level near zero volts. The duration of the signal driven 
high depends on whether the bit value is a Logic 0 or Logic 1. PECI also includes 
variable data transfer rate established with every message. The single wire interface 
provides low board routing overhead for the multiple load connections in the congested 
routing area near the processor and chipset components. Bus speed, error checking, 
and low protocol overhead provides adequate link bandwidth and reliability to transfer 
critical device operating conditions and configuration information.