Intel G1620T CM8063701448300 User Manual

Datasheet

1085

The LSR, line status register shows the current state of communication. Errors are 

reflected in this register. The state of the receive and transmit buffers is also available.

Default: 60h

2

0b

RW

Auxiliary output 1 (OUT1): This is used to directly control the user-designated 

Output1 (out1_n) output. The value written to this location is inverted and driven out on 

out1_n, that is: '0' - out1_n de-asserted (logic 1) '1' - out1_n asserted (logic 0) Note 

that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high 

while the value of this location is internally looped back to an input.

1

0b

RW

Request to Send (RTS): This is used to directly control the Request to Send (rts_n) 

output. The Request To Send (rts_n) output is used to inform the modem or data set 

that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled 

(MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a 

high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and 

FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is 

also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above 

the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in 

Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the 

value of this location is internally looped back to an input. Note that PCU-UART does not 

implement the Request to Send (rts_n) output.

0

0b

RW

Data Terminal Ready (DTR): This is used to directly control the Data Terminal Ready 

(dtr_n) output. The value written to this location is inverted and driven out on dtr_n, 

that is: '0' - dtr_n de-asserted (logic 1) '1' - dtr_n asserted (logic 0) The Data Terminal 

Ready output is used to inform the modem or data set that the UART is ready to 

establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n 

output is held inactive high while the value of this location is internally looped back to an 

input. Note that PCU-UART does not implement the Data Terminal Ready (dtr_n) output.

Type: I/O Register

(Size: 8 bits)

7

4

0

0

1

1

0

0

0

0

0

RFE

TE

M

T

TH

RE

BI

FE

PE

OE

DR

7

0b

RO

Receiver FIFO Error (RFE): This bit is only relevant when FIFO_MODE != NONE AND 

FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one 

parity error, framing error, or break indication in the FIFO. '0' - no error in RX FIFO '1' - 

error in RX FIFO This bit is cleared when the LSR is read and the character with the error 

is at the top of the receiver FIFO and there are no subsequent errors in the FIFO.

6

1b

RO

Transmitter Empty (TEMT): If in FIFO mode (FIFO_MODE != NONE) and FIFOs 

enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and 

the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set 

whenever the Transmitter Holding Register and the Transmitter Shift Register are both 

empty.