Intel G1620T CM8063701448300 User Manual

1086

Datasheet

5

1b

RO

Transmit Holding Register Empty (THRE): If THRE_MODE_USER == Disabled or 

THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/

enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set 

whenever data is transferred from the THR or TX FIFO to the transmitter shift register 

and no new data has been written to the THR or TX FIFO. This also causes a THRE 

Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled 

AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set 

to one respectively), the functionality is switched to indicate the transmitter FIFO is full, 

and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] 

threshold setting.

4

0b

RO

Break Interrupt (BI): This is used to indicate the detection of a break sequence on 

the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the 

serial input, sin, is held in a logic '0' state for longer than the sum of start time + data 

bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever 

the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start 

time + data bits + parity + stop bits. A break condition on serial input causes one and 

only one character, consisting of all zeros, to be received by the UART. In the FIFO 

mode, the character associated with the break condition is carried through the FIFO and 

is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI 

bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the 

LSR is read.

3

0b

RO

Framing Error (FE): This is used to indicate the occurrence of a framing error in the 

receiver. A framing error occurs when the receiver does not detect a valid STOP bit in 

the received data. In the FIFO mode, since the framing error is associated with a 

character received, it is revealed when the character with the framing error is at the top 

of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this 

by assuming that the error was due to the start bit of the next character and then 

continues receiving the other bit; that is, data, and/or parity and stop. It should be 

noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as 

indicated by Break Interrupt (BI) bit (LSR[4]). '0' - no framing error '1' - framing error 

Reading the LSR clears the FE bit.

2

0b

RO

Parity Error (PE): This is used to indicate the occurrence of a parity error in the 

receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity 

error is associated with a character received, it is revealed when the character with the 

parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) 

bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) 

bit (LSR[4]). '0' - no parity error '1' - parity error Reading the LSR clears the PE bit.

1

0b

RO

Overrun Error (OE): This is used to indicate the occurrence of an overrun error. This 

occurs if a new data character was received before the previous data was read. In the 

non-FIFO mode, the OE bit is set when a new character arrives in the receiver before 

the previous character was read from the RBR. When this happens, the data in the RBR 

is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a 

new character arrives at the receiver. The data in the FIFO is retained and the data in 

the receive shift register is lost. '0' - no overrun error '1' - overrun error Reading the 

LSR clears the OE bit.

0

0b

RO

Data Ready (DR): This is used to indicate that the receiver contains at least one 

character in the RBR or the receiver FIFO. '0' - no data ready '1' - data ready This bit is 

cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in 

FIFO mode.