Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – System Management Bus (SMBus)
1110
Datasheet
22.6.18
D31_F3_PID (SMB_Config_CAP_ID)—Offset 50h
Power Management Capability ID
Access Method
Default: 0001h
22.6.19
D31_F3_PC (SMB_Config_PMC)—Offset 52h
Power Management Capabilities
Access Method
Default: 0003h
Type: PCI Configuration Register
(Size: 16 bits)
SMB_Config_CAP_ID: [B:0, D:31, F:3] + 50h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Ne
xt_Item_
Ptr
Cap
_
ID
Bit
Range
Default &
Access
Description
15:8
00h
RO
Next Item Pointer (Next_Item_Ptr): This field provides an offset into the functions
PCI Configuration Space pointing to the location of next item in the functions capability
list. If there are no additional items in the Capabilities List, this register is set to 00h.
7:0
01h
RO
Capability Identifier (Cap_ID): This field, when 01h identifies the linked list item as
being the PCI Power Management registers.
Type: PCI Configuration Register
(Size: 16 bits)
SMB_Config_PMC: [B:0, D:31, F:3] + 52h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
PM
ES
D2S
D1S
AC
DSI
RS
V1
PME
C
VS
Bit
Range
Default &
Access
Description
15:11
00000b
RO
PME_Support (PMES): This 5-bit field indicates the power states in which the function
may assert PME#. A value of 0b for any bit indicates that the function is not capable of
asserting the PME# signal while in that power state. bit(11) X XXX1b - PME# can be
asserted from D0 bit(12) X XX1Xb - PME# can be asserted from D1 bit(13) X X1XXb -
PME# can be asserted from D2 bit(14) X 1XXXb - PME# can be asserted from D3hot
bit(15) 1 XXXXb - PME# can be asserted from D3cold
10
0b
RO
D2_Support (D2S): If this bit is a '1', this function supports the D2 Power
Management State. Functions that do not support D2 must always return a value of '0'
for this bit.
9
0b
RO
D1_Support (D1S): If this bit is a '1', this function supports the D1 Power
Management State. Functions that do not support D2 must always return a value of '0'
for this bit.