Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – System Management Bus (SMBus)
1112
Datasheet
22.6.21
D31_F3_PMCSR_BSE (SMB_Config_PMCSR_BSE)—Offset 56h
PMCSR_BSE supports PCI bridge specific functionality and is required for all PCI-to-PCI
bridges.
Access Method
Default: 00h
22.6.22
D31_F3_DATA (SMB_Config_DATA)—Offset 57h
PMCSR_BSE supports PCI bridge specific functionality and is required for all PCI-to-PCI
bridges.
Access Method
Default: 00h
1:0
00b
RW
PowerState (PS): This 2-bit field is used both to determine the current power state of
a function and to set the function into a new power state. The definition of the field
values is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to
write an unsupported, optional state to this field, the write operation must complete
normally on the bus; however, the data is discarded and no state change occurs.
Bit
Range
Default &
Access
Description
Type: PCI Configuration Register
(Size: 8 bits)
SMB_Config_PMCSR_BSE: [B:0, D:31, F:3] + 56h
7
4
0
0
0
0
0
0
0
0
0
BPCCE
B23
RS
V1
Bit
Range
Default &
Access
Description
7
0b
RO
BPCC_En (BPCCE): Bus Power/Clock Control Enable - Does not apply
6
0b
RO
B2_B3 (B23): B2/B3 support for D3hot - Does not apply
5:0
00h
RO
Reserved (RSV1): Reserved
Type: PCI Configuration Register
(Size: 8 bits)
SMB_Config_DATA: [B:0, D:31, F:3] + 57h
7
4
0
0
0
0
0
0
0
0
0
DT
Bit
Range
Default &
Access
Description
7:0
00h
RO
Data (DT): Data - Does not apply