Intel G1620T CM8063701448300 User Manual

Product codes

CM8063701448300

PCU – System Management Bus (SMBus)

1114

Datasheet

22.7

PCU SMBus Memory Mapped I/O Registers

22.7.1

Host Status Register (SMB_Mem_HSTS)—Offset 0h

All status bits are set by hardware and cleared by the software writing a one to the

particular bit position. Writing a zero to any bit position has no affect

Access Method

Default: 00h

Table 165.

Summary of PCU SMBus Memory Mapped I/O Registers—SMB_Config_MBARL

Offset

Size

Register ID—Description

Default

Value

“Host Status Register (SMB_Mem_HSTS)—Offset 0h” on page 1114

00h

“Host Control Register (SMB_Mem_HCTL)—Offset 2h” on page 1115

00h

“Host Command Register (SMB_Mem_HCMD)—Offset 3h” on page 1117

00h

“Transmit Slave Address Register (SMB_Mem_TSA)—Offset 4h” on page 1117

00h

“Data 0 Register (SMB_Mem_HD0)—Offset 5h” on page 1118

00h

“Data 1 Register (SMB_Mem_HD1)—Offset 6h” on page 1118

00h

“Host Block Data (SMB_Mem_HBD)—Offset 7h” on page 1119

00h

“Packet Error Check Data Register (SMB_Mem_PEC)—Offset 8h” on page 1120

00h

“Auxiliary Status (SMB_Mem_AUXS)—Offset Ch” on page 1120

00h

“Auxiliary Control (SMB_Mem_AUXC)—Offset Dh” on page 1121

00h

“SMBUS_PIN_CTL Register (SMB_Mem_SMBC)—Offset Fh” on page 1121

07h

10h

“Slave Status Register (SMB_Mem_SSTS)—Offset 10h” on page 1122

00h

11h

“Slave Command Register (SMB_Mem_SCMD)—Offset 11h” on page 1122

00h

14h

“Notify Device Address Register (SMB_Mem_NDA)—Offset 14h” on page 1123

00h

16h

“Notify Data Low Byte Register (SMB_Mem_NDLB)—Offset 16h” on page 1124

00h

17h

“Notify Data High Byte Register (SMB_Mem_NDHB)—Offset 17h” on page 1124

00h

Type: Memory Mapped I/O Register

(Size: 8 bits)

SMB_Mem_HSTS: [MBARL] + 0h

MBARL Type: PCI Configuration Register (Size: 32 bits)
MBARL Reference: [B:0, D:31, F:3] + 10h

BDS

SMB_A

LER