Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Processor Transaction Router
118
Datasheet
11.1
Transaction Router C-Unit PCI Configuration Registers
11.1.1
CUNIT_REG_DEVICEID—Offset 0h
CUnit Configuration Register Device ID/Vendor ID. Device ID and Vendor ID Strapped
in from top level. Reset value to strapDID[15:3],fuse[2:0], 16'h8086 these bits can be
re-written from SETIDVALUE message 1st DW data byte 2, byte 3
Access Method
Default: 00008086h
Table 92.
Summary of Transaction Router PCI Configuration Registers—0/0/0
Offset
Size
Register ID—Description
Default
Value
0h
1
00008086h
4h
1
00000007h
8h
1
06000000h
Ch
1
00000000h
2Ch
1
00000000h
F8h
1
00000000h
Type: PCI Configuration Register
(Size: 32 bits)
CUNIT_REG_DEVICEID: [B:0, D:0, F:0] + 0h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0
DEVIC
E
ID_VENDOR_ID
DE
VICEID_BIT
_
22_19
DE
VICEID_BIT
_
18_16
DE
VICEID_BIT_15_0
Bit
Range
Default &
Access
Description
31:23
0h
RW
DEVICEID_VENDOR_ID: Device ID and Vendor ID bit [15:7] are strapped in from top
level. These bits can be re-written from SETIDVALUE message 1st DW data byte 2, byte
3. for VLV/VLV2, final setting of this field is from SETIDVALUE message, while for TNG it
uses the strapped setting. For all processor's, the RDL default is set to the strapped
setting in that processor. Please refer to the processor documentation to determine the
proper Device ID for the chip.
22:19
0h
RO
DEVICEID_bit_22_19 (DEVICEID_BIT_22_19): Device ID [6:3] Hardwired in the
design. SETIDVALUE message will not re-write this field. RDL default is set to the
strapped value
18:16
0h
RO
DEVICEID_bit_18_16 (DEVICEID_BIT_18_16): Device ID [2:0]. Strapped in from
top level and tied to fuses to determine product SKU. SETIDVALUE message will not re-
write this field.
15:0
8086h
RO
DEVICEID_bit_15_0 (DEVICEID_BIT_15_0): Hardwired