Intel G1620T CM8063701448300 User Manual

1254

Datasheet

The processor cascades the slave controller onto the master controller through master 
controller interrupt input 2. This means there are only 15 possible interrupts for the 
processor PIC.

Interrupts can be programmed individually to be edge or level, except for IRQ0, IRQ2, 
and IRQ8#.

Active-low interrupt sources (such as a PIRQ#) are inverted inside the processor. In the 
following descriptions of the 8259s, the interrupt levels are in reference to the signals 
at the internal interface of the 8259s, after the required inversions have occurred. 
Therefore, the term “high” indicates “active,” which means “low” on an originating 
PIRQ#.

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each 
interrupt level. These bits are used to determine the interrupt vector returned, and 
status of any other pending interrupts. 

 defines the IRR, ISR, and IMR.

The processor generates an interrupt acknowledge cycle that is translated into a 
Interrupt Acknowledge Cycle to the processor. The PIC translates this command into 
two internal INTA# pulses expected by the 8259 controllers. The PIC uses the first 

Slave

0

Inverted IRQ8# from internal RTC or HPET

1

IRQ9 via SERIRQ, SCI or PIRQx

2

IRQ10 via SERIRQ, SCI or PIRQx

3

IRQ11 via SERIRQ, SCI, HPET or PIRQx

4

IRQ12 via SERIRQ, PIRQx or mouse emulation

5

None

6

PIRQx or IRQ14 from SATA controller

7

IRQ15 via SERIRQ or PIRQx or IRQ15 from SATA controller

IRR

Interrupt Request Register. This bit is set on a low-to-high transition of the interrupt line in edge 

mode, and by an active high level in level mode.

ISR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an 

interrupt acknowledge cycle is seen, and the vector returned is for that interrupt.

IMR

Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts 

will not generate INTR.