Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
1256
Datasheet
31.1.2
Initialization Command Words (ICWx)
Before operation can begin, each 8259 must be initialized. In the processor, this is a
four-byte sequence. The four initialization command words are referred to by their
acronyms: ICW1, ICW2, ICW3, and ICW4.
four-byte sequence. The four initialization command words are referred to by their
acronyms: ICW1, ICW2, ICW3, and ICW4.
The base address for each 8259 initialization command word is a fixed location in the
I/O memory space: 20h for the master controller, and A0h for the slave controller.
I/O memory space: 20h for the master controller, and A0h for the slave controller.
31.1.2.1
ICW1
A write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, the PIC expects three more
byte writes to 21h for the master controller, or A1h for the slave controller, to complete
the ICW sequence.
interpreted as a write to ICW1. Upon sensing this write, the PIC expects three more
byte writes to 21h for the master controller, or A1h for the slave controller, to complete
the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
automatically occur:
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
transition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
31.1.2.2
ICW2
The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
31.1.2.3
ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
•
For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the processor, IRQ2 is used. Therefore,
MICW3.CCC is set to a 1, and the other bits are set to 0s.
cascade the slave controller. Within the processor, IRQ2 is used. Therefore,
MICW3.CCC is set to a 1, and the other bits are set to 0s.
•
For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller if the cascaded interrupt won
arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and if it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller if the cascaded interrupt won
arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and if it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.