Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
1258
Datasheet
31.1.4.3
Automatic Rotation Mode (Equal Priority Devices)
In some applications, there are a number of interrupting devices of equal priority.
Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a
device receives the lowest priority after being serviced. In the worst case, a device
requesting an interrupt has to wait until each of seven other devices are serviced at
most once.
Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a
device receives the lowest priority after being serviced. In the worst case, a device
requesting an interrupt has to wait until each of seven other devices are serviced at
most once.
There are two ways to accomplish automatic rotation using OCW2.REOI; the Rotation
on Non-Specific EOI Command (OCW2.REOI=101b) and the rotate in automatic EOI
mode which is set by (OCW2.REOI=100b).
on Non-Specific EOI Command (OCW2.REOI=101b) and the rotate in automatic EOI
mode which is set by (OCW2.REOI=100b).
31.1.4.4
Specific Rotation Mode (Specific Priority)
Software can change interrupt priorities by programming the bottom priority. For
example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest
priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:
OCW2.REOI=11xb, and OCW2.ILS is the binary priority level code of the bottom
priority device.
example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest
priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:
OCW2.REOI=11xb, and OCW2.ILS is the binary priority level code of the bottom
priority device.
In this mode, internal status is updated by software control during OCW2. However, it
is independent of the EOI command. Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI Command in OCW2 (OCW2.REOI=111b)
and OCW2.ILS=IRQ level to receive bottom priority.
is independent of the EOI command. Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI Command in OCW2 (OCW2.REOI=111b)
and OCW2.ILS=IRQ level to receive bottom priority.
31.1.4.5
Poll Mode
Poll mode can be used to conserve space in the interrupt vector table. Multiple
interrupts that can be serviced by one interrupt service routine do not need separate
vectors if the service routine uses the poll command. Poll mode can also be used to
expand the number of interrupts. The polling interrupt service routine can call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
interrupts that can be serviced by one interrupt service routine do not need separate
vectors if the service routine uses the poll command. Poll mode can also be used to
expand the number of interrupts. The polling interrupt service routine can call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting OCW3.PMC. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in Bit 7 if there is an interrupt, and the binary
code of the highest priority level in Bits 2:0.
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in Bit 7 if there is an interrupt, and the binary
code of the highest priority level in Bits 2:0.
31.1.4.6
Edge and Level Triggered Mode
In ISA systems this mode is programmed using ICW1.LTIM, which sets level or edge for
the entire controller. In the processor, this bit is disabled and a register for edge and
level triggered mode selection, per interrupt input, is included. This is the Edge/Level
control Registers ELCR1 and ELCR2.
the entire controller. In the processor, this bit is disabled and a register for edge and
level triggered mode selection, per interrupt input, is included. This is the Edge/Level
control Registers ELCR1 and ELCR2.