Intel G1620T CM8063701448300 User Manual

Datasheet

141

Default: 0000h

Type: PCI Configuration Register

(Size: 16 bits)

15

12

8

4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RSV

D

0

ID

FBE

SEE

WC

C

PE

E

VGA

MWI

E

SC

E

BM

E

MSE

IOSE

15:11

0b

RO

RSVD0: Reserved

10

0h

RW

Interrupt Disable (ID): This disables pin-based INTx# interrupts. This bit has no 

effect on MSI operation. When set, internal INTx# will not be generated. When cleared, 

internal INTx# is generated if there is an interrupt and MSI is not enabled.

9

0h

RO

Fast Back-to-Back Enable (FBE): Reserved.

8

0h

RW

SERR# Enable (SEE): When set to 1, the HBA is allowed to generate SERR# on DPD or 

SATAGC.URD event that is enabled for SERR# generation. When cleared to 0, it is not.

7

0h

RO

Wait Cycle Enable (WCC): Reserved.

6

0h

RW

Parity Error Response Enable (PEE): When set, the SATA Controller will corrupt the 

outbound DATA FIS CRC if a forwarded data parity error is indicated.

5

0h

RO

VGA Palette Snooping Enable (VGA): Reserved.

4

0h

RO

Memory Write and Invalidate Enable (MWIE): Reserved.

3

0h

RO

Special Cycle Enable (SCE): Reserved.

2

0h

RW

Bus Master Enable (BME): Controls the SATA Controller's ability to act as a master for 

data transfers. This bit does not impact the generation of completions for split 

transaction commands.

1

0h

RW

Memory Space Enable (MSE): Controls access to the SATA Controller's target 

memory space (for AHCI).

0

0h

RW

I/O Space Enable (IOSE): Controls access to the SATA Controller's target I/O space.