Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Serial ATA (SATA)
142
Datasheet
13.5.3
Device Status (STS)—Offset 6h
Access Method
Default: 02B0h
Type: PCI Configuration Register
(Size: 16 bits)
15
12
8
4
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
DPE
SS
E
RMA
RT
A
ST
A
DEV
T
DPD
FBC
RSV
D
0
RS
V
CL
IS
RSV
D
1
Bit
Range
Default &
Access
Description
15
0h
RW/1C
Detected Parity Error (DPE): Set when the SATA Controller detects a parity error on
its interface.
14
0h
RW/1C
Signaled System Error (SSE): Set when SATA Controller generates an SERR#.
13
0h
RW/1C
Received Master-Abort Status (RMA): Set when the SATA Controller receives a
master abort to a cycle it generated.
12
0h
RW/1C
Received Target-Abort Status (RTA): Set when the SATA Controller receives a target
abort to a cycle it generated.
11
0h
RW/1C
Signaled Target-Abort Status (STA): This bit must be set by a target device
whenever it terminates a transaction with Target-Abort. Devices that will never signal
Target-Abort do not need to implement this bit.
10:9
1h
RO
DEVSEL# Timing Status (DEVT): Controls the device select time for the SATA
Controller's PCI interface.
8
0h
RW/1C
Master Data Parity Error Detected (DPD): Set when the SATA Controller, as a
master, either detects a parity error or sees the parity error line asserted, and the parity
error response bit (bit 6 of the command register) is set. This bit can only be set on read
completions received from the backbone where there is a parity error.
7
1h
RO
Fast Back-to-Back Capable (FBC): Reserved.
6
0b
RO
RSVD0: Reserved
5
1h
RO
66 MHz Capable (RSV): Reserved.
4
1h
RO
Capabilities List (CL): Indicates the presence of a capabilities list. The minimum
requirement for the capabilities list must be PCI power management for the SATA
Controller.
3
0h
RO
Interrupt Status (IS): Reflects the state of INTx# messages, IRQ14 or IRQ15. This bit
is set when the interrupt is to be asserted. This bit is a 0 after the interrupt is cleared
2:0
0b
RO
RSVD1: Reserved