Intel G1620T CM8063701448300 User Manual

346

Datasheet

Default: 0290h

4

0b

RO

Memory Write Invalidate (MWI): Reserved.

3

0b

RO

Special Cycle Enable (SCE): Reserved.

2

0b

RW

Bus Master Enable (BME): When set, it allows XHC to act as a bus master. When 

cleared, it disable XHC from initiating transactions on the system bus.

1

0b

RW

Memory Space Enable (MSE): This bit controls access to the XHC Memory Space 

registers. If this bit is set, accesses to the XHC registers are enabled. The Base Address 

register for the XHC should be programmed before this bit is set.

0

0b

RO

I/O Space Enable (IOSE): Reserved as 0. Read-Only.

Type: PCI Configuration Register

(Size: 16 bits)

Power Well: Core

15

12

8

4

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

0

0

DPE

SSE

RMA

RT

A

ST

A

DEV

T

MD

PE

D

FBBC

UDF

MC

CL

IS

RSV

D

15

0b

RW/1C

Detected Parity Error (DPE): This bit is set by the Intel PCH whenever a parity error 

is seen on the internal interface to the XHC host controller, regardless of the setting of 

bit 6 or bit 8 in the Command register or any other conditions. Software clears this bit 

by writing a 1 to this bit location.

14

0b

RW/1C

Signaled System Error (SSE): This bit is set by the Intel PCH whenever it signals 

SERR# (internally). The SERR_EN bit (bit 8 in the Command Register) must be 1 for this 

bit to be set. See error handling section for complete list of conditions handled. Software 

clears this bit by writing a 1 to this bit location.

13

0b

RW/1C

Received Master-Abort Status (RMA): This bit is set when XHC, as a master, 

receives a master-abort status on a memory access. This is treated as a Host Error and 

halts the DMA engines. Software clears this bit by writing a 1 to this bit location.

12

0b

RW/1C

Received Target Abort Status (RTA): This bit is set when XHC, as a master, receives 

a target abort status on a memory access. This is treated as a Host Error and halts the 

DMA engines. Software clears this bit by writing a 1 to this bit location.

11

0b

RW/1C

Signaled Target-Abort Status (STA): This bit is used to indicate when the XHC 

function responds to a cycle with a target abort.

10:9

01b

RO

DEVSEL# Timing Status (DEVT): This 2-bit field defines the timing for DEVSEL# 

assertion. Read-Only.

8

0b

RW/1C

Master Data Parity Error Detected (MDPED): This bit is set by the Intel PCH 

whenever a data parity error is detected on a XHC read completion packet on the 

internal interface to the XHC host controller and bit 6 of the Command register is set to 

1. Software clears this bit by writing a 1 to this bit location.