Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Datasheet
961
PCU – Power Management Controller (PMC)
If PMC_PWRBTN# is observed active for at least four consecutive seconds, the state
machine should unconditionally transition to the S5 state, regardless of present state
(S0–S4), even if the PMC_CORE_PWROK is not active. In this case, the transition to the
G2/S5 state should not depend on any particular response from the processor nor any
similar dependency from any other subsystem.
machine should unconditionally transition to the S5 state, regardless of present state
(S0–S4), even if the PMC_CORE_PWROK is not active. In this case, the transition to the
G2/S5 state should not depend on any particular response from the processor nor any
similar dependency from any other subsystem.
The PMC_ PWRBTN# status is readable to check if the button is currently being pressed
or has been released. The status is taken after the de-bounce, and is readable using
the GEN_PMCON2.PWRBTN_LVL bit.
or has been released. The status is taken after the de-bounce, and is readable using
the GEN_PMCON2.PWRBTN_LVL bit.
Note:
The 4-second PMC_PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the processor is in a S0 state. If the
PMC_PWRBTN# signal is asserted and held active when the system is in a suspend
state (S3–S4), the assertion causes a wake event. Once the system has resumed to the
S0 state, the 4-second timer starts.
occurred. The 4-second timer starts counting when the processor is in a S0 state. If the
PMC_PWRBTN# signal is asserted and held active when the system is in a suspend
state (S3–S4), the assertion causes a wake event. Once the system has resumed to the
S0 state, the 4-second timer starts.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by GEN_PMCON1.S4ASE), the power button is not a wake event. As a
result, it is conceivable that the user will press and continue to hold the power button
waiting for the system to awake. Since a 4-second press of the power button is already
defined as an unconditional power down, the power button timer will be forced to
inactive while the power-cycle timer is in progress. Once the power-cycle timer has
expired, the power button awakes the system. Once the minimum PMC_SLP_S4#
power cycle expires, the power button must be pressed for another 4 to 5 seconds to
create the override condition to S5.
(if enabled by GEN_PMCON1.S4ASE), the power button is not a wake event. As a
result, it is conceivable that the user will press and continue to hold the power button
waiting for the system to awake. Since a 4-second press of the power button is already
defined as an unconditional power down, the power button timer will be forced to
inactive while the power-cycle timer is in progress. Once the power-cycle timer has
expired, the power button awakes the system. Once the minimum PMC_SLP_S4#
power cycle expires, the power button must be pressed for another 4 to 5 seconds to
create the override condition to S5.
19.2.3.2
Sleep Button
The Advanced Configuration and Power Interface specification defines an optional sleep
button. It differs from the power button in that it only is a request to go from S0 to S3–
S4 (not S5). Also, in an S5 state, the power button can wake the system, but the sleep
button cannot.
button. It differs from the power button in that it only is a request to go from S0 to S3–
S4 (not S5). Also, in an S5 state, the power button can wake the system, but the sleep
button cannot.
Although the processor does not include a specific signal designated as a sleep button,
one of the GPIO signals can be used to create a “Control Method” sleep button. See the
Advanced Configuration and Power Interface specification for implementation details.
one of the GPIO signals can be used to create a “Control Method” sleep button. See the
Advanced Configuration and Power Interface specification for implementation details.
19.2.3.3
PME_B0 (PCI Power Management Event Bus 0)
The GPE0a_STS.PME_B0_STS bit exists to implement PME#-like functionality for any
internal device on Bus 0 with PCI power management capabilities.
internal device on Bus 0 with PCI power management capabilities.
19.2.3.4
PMC_RSTBTN# Signal
When the PMC_RSTBTN# pin is detected as active after the 16 ms debounce logic, the
processor attempts to perform a “graceful” reset, by waiting for the relevant internal
devices to signal their idleness. If all devices are idle when the pin is detected active,
the reset occurs immediately; otherwise, a counter starts. If at any point during the
count all devices go idle the reset occurs. If the counter expires and any device is still
active, a reset is forced upon the system even though activity is still occurring.
processor attempts to perform a “graceful” reset, by waiting for the relevant internal
devices to signal their idleness. If all devices are idle when the pin is detected active,
the reset occurs immediately; otherwise, a counter starts. If at any point during the
count all devices go idle the reset occurs. If the counter expires and any device is still
active, a reset is forced upon the system even though activity is still occurring.