Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
136
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.16 TCDBP
Timing Constraints DDR3 Bin Parameter.
13.2.4.17 TCRAP
Timing Constraints DDR3 Regular Access Parameter. 
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x200
Bit
Attr
Default
Description
31:27
RV
-
Reserved.
26:26
RW
0x0
cmd_oe_cs:
25:25
RW
0x0
cmd_oe_on:
24:19
RW
0x1c
T_RAS (t_ras):
18:14
RW
0x7
T_CWL (t_cwl):
13:9
RW
0xa
T_CL (t_cl):
8:5
RW
0xa
T_RP (t_rp):
4:0
RW
0xa
T_RCD (t_rcd):
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device:
30Function:0,1,4,5
Offset:
0x204
Bit
Attr
Default
Description
31:30
RW
0x0
CMD_STRETCH (cmd_stretch):
defines for how many cycles the command is stretched
00: 1N operation
01: Reserved
10: 2N operation
11: 3N operation
29:29
RV
-
Reserved2:
Reserved.
28:24
RW
0xc
T_WR (t_wr):
WRITE recovery time (must be at least 15ns equivalent)
23:22
RW
0x1
T_PRPDEN (t_prpden):
tPRPDEN, tACTPDEN, tREFPDEN will use this single value. It only needs to have 
value of 2+ for DDR3 2133+.
21:16
RW
0x20
T_FAW (t_faw):
Four activate window (must be at least 4 * tRRD and at most 63)
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