Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
185
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.7.4.5
CAPID3
This register is a Capability Register used to expose enable/disable features for BIOS.
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
3
Offset:
0x90
Bit
Attr
Default
Description
31:30
RO_FW
0x0
MC_SPARE:
29:24
RO_FW
0x0
MC2GD:
MC2GD Bit[5:4]: Tx Pulse Width Control Bit[1:0]. 00 = Short, 01 = Medium, 10 
= Long, 11 = Reserved
MC2GDBit3: DLL VRM: Increase Resistance in the VRM Feedback loop 
MC2GDBit2: DLL VRM: Increase Amp Current in the VRM Feedback loop 
MC2GDBit1: DLL Startup Time setting. 1 = 16cycles, 0 = 32cycles 
MC2GDBit0: 1.35V DDR3L LVDDR disable
23:23
RO_FW
0x0
DISABLE MONROE TECHNOLOGY (DISABLE_MONROE):
Monroe Technology Disable download. When set, the 
MONROE_CHN_FORCE_SR register field in MCMTR and the channel 
MCMTR_SHDW becomes read-only.
22:22
RO_FW
0x0
DISABLE_SMBUS_WRT:
SMBUS write capability disable control. When set, SMBus write is disabled.
21:21
RO_FW
0x0
DISABLE_ROL_OR_ADR:
RAID-On-LOAD disable control. When set, memory ignores ADR event.  
download may change the default value after reset deassertion.
20:20
RO_FW
0x0
DISABLE_EXTENDED_ADDR_DIMM:
Extended addressing DIMM disable control. When set, DIMM with extended 
addressing (MA[17/16] is forced to be zero when driving MA[17:16]).  
19:19
RO_FW
0x0
DISABLE_EXTENDED_LATENCY_DIMM:
extended latency DIMM disable control. When set, DIMM with extended latency 
is forced to CAS to be less than or equal to 14. 
18:18
RO_FW
0x0
DISABLE_PATROL_SCRUB:
 Patrol scrub disable control. When set, rank patrol scrub is disabled. 
17:17
RO_FW
0x0
DISABLE_SPARING:
Sparing disable control. When set, rank sparing is disabled. 
16:16
RO_FW
0x0
DISABLE_LOCKSTEP:
LOCKSTEP disable control. When set, channel lockstep operation is disabled by 
forcing independent channel mode. 
15:15
RO_FW
0x0
DISABLE_CLTT:
CLTT disable control. When set, CLTT support is disabled by disabling TSOD 
polling. 
14:14
RO_FW
0x0
DISABLE_UDIMM:
UDIMM disable control. When set, UDIMM support is disabled by disabling 
address bit swizzling. 
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