Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
195
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.2
DID
14.2.3
PCICMD
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x2
Bit
Attr
Default
Description
15:0
RO
RO_V (Device 0 
and 3 Function 0)
For Device 0 Function 0:
0xe00 (DMI2 Mode)
0xe01 (PCIe* Mode)
For Device 2:
0xe04 (Function 0)
0xe05 (Function 1)
0xe06 (Function 2)
0xe07 (Function 3)
For Device 3:
0xe08 (Function 0)
0xe09 (Function 1)
0xe0a (Function 2)
0xe0b (Function 3)
device_identification_number:
Device ID values vary from function to function. Bits 
15:8 are equal to 0x0E.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x4
Bit
Attr
Default
Description
15:11
RV
-
Reserved. 
10:10
RW
0x0
interrupt_disable:
Interrupt Disable. Controls the ability of the PCI Express port to 
generate INTx messages. This bit does not affect the ability of the 
processor to route interrupt messages received at the PCI Express 
port. However, this bit controls the generation of legacy interrupts 
to the DMI for PCI Express errors detected internally in this port (for 
example, Malformed TLP, CRC error, completion timeout, and so 
forth) or when receiving RP error messages or interrupts due to Hot 
Plug/PM events generated in legacy mode within the processor. 
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
9:9
RO
0x0
fast_back_to_back_enable:
Fast Back-to-Back Enable  
Not applicable to DMI or PCI Express and is hardwired to 0. 
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