Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
197
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
2:2
RW
RO (Device 0 
Function 0 DMI 
mode)
0x0
bme:
Bus Master Enable.
Controls the ability of the PCI Express port in generating and also in 
forwarding memory (including MSI writes) or I/O transactions (and 
not messages) or configuration transactions from the secondary 
side to the primary side. 
1: Enables the PCI Express port to 
a) generate MSI writes internally for AER/Hot Plug/ PM events 
(note: there are several other RP MSI related control/enable bits. 
See the RAS Chapter and PCI Express Base Specification, Revision 
2.0 for complete details) and also to 
b) forward memory (including MSI writes from devices south of the 
RP), config or I/O read/write requests from secondary to primary 
side 
0: The Bus Master is disabled. When this bit is 0, IIO root ports will 
a) treat upstream PCI Express memory writes/reads, IO 
writes/reads, and configuration reads and writes as unsupported 
requests (and follow the rules for handling unsupported requests). 
This behavior is also true towards transactions that are already 
pending in the IIO root port’s internal queues when the BME bit is 
turned off.
b) mask the root port from generating MSI writes internally for 
AER/Hot Plug/PM events at the root port. 
1:1
RW
RO (Device 0 
Function 0 DMI 
mode)
0x0
mse:
Memory Space Enable.
1: Enables a PCI Express port’s memory range registers to be 
decoded as valid target addresses for transactions from secondary 
side.
0: Disables a PCI Express port’s memory range registers (including 
the Configuration Registers range registers) to be decoded as valid 
target addresses for transactions from secondary side. All memory 
accesses received from secondary side are UR’ed.
0:0
RW
RO (Device 0 
Function 0 DMI 
mode)
0x0
iose:
I/O Space Enable  
Controls a device’s response to I/O Space accesses. 
1: Enables the I/O address range, defined in the IIOBASE and IOLIM 
registers of the PCI-PCI bridge header, for target decode from 
primary side.
0: Disables the I/O address range, defined in the IOBASE and IOLIM 
registers of the PCI-to-PCI bridge header, for target decode from 
primary side.
Notes:
This is bit is not ever used by hardware to decode transactions from 
the secondary side of the root port.
This bit is hardwired to 0 in DMI Mode, since the DMI is not a P2P 
bridge and does not claim any IO resource on its own. Hardware 
should not use this bit to determine if it can forward memory 
requests to DMI while in DMI Mode.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x4
Bit
Attr
Default
Description
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