Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
203
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.14 IOBAS
I/O Base Register.
14.2.15 IOLIM
I/O Limit Register.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x1c
Bit
Attr
Default
Description
7:4
RW
0xf
i_o_base_address:
Corresponds to A[15:12] of the I/O base address of the PCI Express port. 
See also the IOLIM register description.
3:2
RW_L
0x0
more_i_o_base_address:
When EN1K is set in the IIOMISCCTRL register, these bits become RW and 
allow for 1K granularity of I/O addressing, otherwise these are RO.
Note: To write this field, the bit 0 of LT_MEMORY_LOCK (MSR 0x2e7) must be 
0 also. 
1:0
RO
0x0
i_o_address_capability:
IIO supports only 16 bit addressing
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x1d
Bit
Attr
Default
Description
7:4
RW
0x0
i_o_address_limit:
Corresponds to A[15:12] of the I/O limit address of the PCI Express port.The 
I/O Base and I/O Limit registers define an address range that is used by the 
PCI Express port to determine when to forward I/O transactions from one 
interface to the other using the following formula:
IO_BASE <= A[15:12] <= IO_LIMIT
The bottom of the defined I/O address range will be aligned to a 4KB 
boundary (1KB if EN1K bit is set. Refer to the IIOMISCCTRL register for 
definition of EN1K bit) while the top of the region specified by IO_LIMIT will 
be one less than a 4 KB (1KB if EN1K bit is set) multiple.
Notes:
Setting the I/O limit less than I/O base disables the I/O range altogether.
General the I/O base and limit registers won’t be programmed by software 
without clearing the IOSE bit first.
3:2
RW_L
0x0
more_i_o_address_limit:
When EN1K is set in the IIOMISCCTRL register, these bits become RW and 
allow for 1K granularity of I/O addressing, otherwise these are RO.
Note: To write this field, the bit 0 of LT_MEMORY_LOCK (MSR 0x2e7) must be 
0 also.
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