Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
205
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.17 MBAS
Memory Base.
8:8
RW1C
0x0
mdpe:
Master Data Parity Error  
This bit is set by the root port on the secondary side (PCI Express link) if the 
Parity Error Response Enable bit (PERRE) is set in Bridge Control register and 
either of the following two conditions occurs:
The PCI Express port receives a Completion from PCI Express marked 
poisoned.
The PCI Express port poisons an outgoing packet with data.
If the Parity Error Response Enable bit in Bridge Control Register is cleared, 
this bit is never set.
7:7
RO
0x0
fast_back_to_back_transactions_capable:
Not applicable to PCI Express. Hardwired to 0.
6:6
RV
-
Reserved. 
5:5
RO
0x0
pci66_mhz_capability:
Not applicable to PCI Express. Hardwired to 0.
4:0
RV
-
Reserved. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x1e
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x20
Bit
Attr
Default
Description
15:4
RW
0xfff
memory_base_address:
Corresponds to A[31:20] of the 32 bit memory window’s base address of the 
PCI Express port. See also the MLIM register description.
3:0
RV
-
Reserved. 
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