Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
244
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.59 PMCAP
Power Management Capabilities
The PM Capabilities Register defines the capability ID, next pointer and other power 
management related support. The following PM registers/capabilities are 
added for 
software compliance.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xe0
Bit
Attr
Default
Description
31:27
RO_V
0x0 
(Device 0 Function 0 DMI mode) 
0x19 
(Device 0 Function 0 PCIe* mode,
Device 2, Device 3)
pme_support:
For Device 0 Function 0 DMI mode,
Bit 31, 30 and 27 must be ‘0’. PME is not supported 
in this device/function.
For Device 0 Function 0 PCIe* mode, Device 2 and 
Device 3,
Bits 31, 30 and 27 must be set to ‘1’ for PCI-PCI 
bridge structures representing ports on root 
complexes.
26:26
RO
0x0
d2_support:
I/OxAPIC does not support power management 
state D2.
25:25
RO
0x0
d1_support:
I/OxAPIC does not support power management 
state D1.
24:22
RO
0x0
aux_current:
21:21
RO
0x0
device_specific_initialization:
20:20
RV
-
Reserved.
19:19
RO
0x0
pme_clock:
This field is hardwired to 0h as it does not apply to 
PCI Express.
18:16
RO
0x3
version:
This field is set to 3h (PM 1.2 compliant) as version 
number. Bit is RW_O to make the version 2h incase 
legacy OSes have any issues.
15:8
RO
0x0
next_capability_pointer:
This is the last capability in the chain and hence set 
to 0.
7:0
RO
0x1
capability_id:
Provides the PM capability ID assigned by PCI-SIG.
downloadlike
ArtboardArtboardArtboard
Report Bug