Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
259
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.82 PERFCTRLSTS_0
Performance Control and Status Register 0.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x180
Bit
Attr
Default
Description
31:21
RV
-
Reserved.
20:16
RW
0x18
outstanding_requests_gen1:
15:14
RV
-
Reserved.
13:8
RW
0x30
outstanding_requests_gen2:
7:7
RW
0x1
use_allocating_flow_wr:
Use Allocating Flows for ‘Normal Writes’ on VC0 and VCp  
1: Use allocating flows for the writes that meet the following criteria.
0: Use nonallocating flows for writes that meet the following criteria.
(TPH=0 OR TPHDIS=1 OR (TPH=1 AND Tag=0 AND CIPCTRL[28]=1)) AND
(NS=0 OR NoSnoopOpWrEn=0) AND 
Non-DCA Write
Note:
VC1/VCm traffic is not impacted by this bit in Dev#0
When allocating flows are used for the above write types, IIO does not send 
a Prefetch Hint message.
Current recommendation for BIOS is to just leave this bit at default of 1b for 
all but DMI port. For DMI port when operating in DMI mode, this bit must be 
left at default value and when operating in PCIe* mode, this bit should be set 
by BIOS.
Note there is a coupling between the usage of this bit and bits 2 and 3. 
TPHDIS is bit 0 of this register
NoSnoopOpWrEn is bit 3 of this register
6:6
RW
0x0
vcp_roen_nswr:
Only available for Device 0 Function 0.
5:5
RW
0x0
vcp_nsen_rd:
Only available for Device 0 Function 0.
4:4
RW
0x1
read_stream_interleave_size:
3:3
RW
0x0
nosnoopopwren:
Enable No-Snoop Optimization on VC0 writes and VCp writes  
This applies to writes with the following conditions:
   NS=1 AND (TPH=0 OR TPHDIS=1)
1: Inbound writes to memory with above conditions will be treated as 
noncoherent (no snoops) writes on Intel
®
QPI
0: Inbound writes to memory with above conditions will be treated as 
allocating or nonallocating writes, depending on bit 4 in this register.
If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored
VC1/VCm writes are not controlled by this bit since they are always non-
snoop and can be no other way.
Current recommendation for BIOS is to just leave this bit at default of 0b.
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