Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
292
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13:11
RW
0x0
counter_enable_source:
Counter enable source  
These bits identify which input enables the counter. Default value disables 
counting.
000: Disabled
001: Local Count Enabled (LCEN). This bit is always a logic 1.
010: Partner counter’s event status (max compare or overflow)
011: Reserved
100: GE[0], from the Global Debug Event Block
101: GE[1], from the Global Debug Event Block
110: GE[2], from the Global Debug Event Block
111: GE[3], from the Global Debug Event Block
Note: Address/Header MatchOut signal must align with PMEVL,H events for 
this to be effective. 
10:8
RW
0x0
reset_event_select:
Reset Event Select  
Counter and event status will reset and counting will continue. 
000: No reset condition
001: Partner’s event status: When the partner counter causes an event status 
condition to be activated, either by a counter overflow or max comparison, 
then this counter will reset and continue counting.
010: Partners PME register event: When the partner counter detects a match 
condition which meets its selected PME register qualifications, then this 
counter will reset and continue counting.
011: This PM counter’s status output.
100: GE[0], from the Global Debug Event Block.
101: GE[1], from the Global Debug Event Block.
110: GE[2], from the Global Debug Event Block.
111: GE[3], from the Global Debug Event Block. 
7:6
RW
0x0
compare_mode:
Compare Mode  
This field defines how the PMC (compare) register is to be used.
00: compare mode disabled (PMC register not used)
01: max compare only: The PMC register value is compared with the counter 
value. If the counter value is greater then the Compare Status (CMPSTAT) will 
be set.
10: max compare with update of PMC at end of sample: The PMC register 
value is compared with the counter value, and if the counter value is greater, 
the PMC register is updated with the counter value. Note, the Compare Status 
field is not affected in this mode.
11: Reserved 
5:5
RW
0x0
pm_status_signal_output:
PM Status Signal Output  
0: Level output from status/overflow signals.
1: Pulsed output from status/overflow signals. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x494, 0x498
Bit
Attr
Default
Description
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