Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
315
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.4.8
HDR
14.4.9
CB_BAR
Intel® Quick Data Base Address Register.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0xe
Bit
Attr
Default
Description
7:7
RO
0x1
multi_function_device:
This bit defaults to 1b since all these devices are multifunction
6:0
RO
0x0
configuration_layout:
This field identifies the format of the configuration header layout. It is Type 0 
for all these devices. The default is 00h, indicating a “endpoint device”.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x10
Bit
Attr
Default
Description
63:14
RW
0x0
bar:
This marks the 16 KB aligned 64-bit base address for memory-mapped 
registers of Intel® Quick Data DMA Through the rest of the CSPEC, the BAR 
register in the 8 functions will be referenced with a logical name of 
CB_BAR[0:7].
Note that accesses to registers pointed to by the CB_BAR, via message 
channel or JTAG mini-port are not gated by the Memory Space Enable (MSE) 
bit in the PCICMD register of the particular function. I.E. accesses via these 
two paths (which are used for internal micro-code/PCU microcode and JTAG) 
to the CB_BAR registers are honored regardless of the setting of MSE bit
13:4
RV
-
Reserved. 
3:3
RO
0x0
prefetchable:
The DMA registers are not prefetchable.
2:1
RO
0x2
type:
The DMA registers is 64-bit address space and can be placed anywhere within 
the addressable region of the system.
0:0
RO
0x0
memory_space:
This Base Address Register indicates memory space.
downloadlike
ArtboardArtboardArtboard
Report Bug