Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
33
Datasheet Volume Two: Functional Description, February 2014
Cbo Functional Description
3.2.6
TSEG Range (CSR_TSEG <= addr)
The TSEG range is used to manage the SMM memory region for DMA accesses. The 
protection is done by the core (through SMRR) and the IIO (through registers) thus it is 
not the responsibility of the uncore Cbo SAD.
3.2.7
Configuration Address Space
Configuration accesses to Uncore control registers are originally in the I/O address 
space. There is also a range for PCI Express* configuration registers access in the 
memory address space. 
Note that Legacy PCI configuration register accesses are done using I/O accesses to 
CFC/CF8. These PCI configuration accesses are translated to PCI Express configuration 
accesses by CPU.
3.2.8
NO_EGO Range
NO_EGO range in Intel Xeon processor E7 v2 product family is 32 MB in size and will 
contain Flash, ICH, LT, IOAPIC and Abort regions as specified in the following 
subsections. Access to undefined region in NO_EGO range will be aborted by the 
processor and will not result in alias access to DRAM or MMIO range. 
3.2.9
I/O Address Space
The processor's I/O address space is used for VGA aliasing, CFC/CF8 accesses for the 
configuration space of PCI Express segment 0, and other I/O devices.
3.2.10
SAD Glossary
ASEG – CSEG is sometimes called the ASEG because it is located at A_0000 segment 
in memory.
CSEG – An uncacheable, compatibility segment used for 16b code for system 
management mode and SMI handlers for patches. 
HOM – The coherent Intel QPI channel.
MMIO – Memory Mapped I/O
NC – Non-coherent Intel QPI channel
PAM – Legacy BIOS ROM area in MMIO and when overlaid with DRAM it is used as a 
faster ROM storage area.
SMM – System Management Mode
SMRR – System Management Mode Range Register
TSEG – A cacheable region of DRAM used for 32b code for SMM
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