Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
339
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.5.10 DCAOFFSET
3:3
RO
0x0
xor:
If set, specifies XOR opcodes are supported. Opcodes are:
0x85 - original XOR Generation
0x86 - original XOR Validate
Notes:
These opcodes have been deprecated in Intel® Quick Data DMA 
v3.
The DMA engine will abort if it encounters a descriptor with these 
opcodes.
2:2
RO
0x1
marker_skipping:
If set, specifies the Marker Skipping opcode is supported. The 
opcode is:
0x84 - Marker Skipping
Notes:
When this bit is zero, the DMA engine will abort if it encounters a 
descriptor with this opcode.
1:1
RO
0x1
crc:
If set, specifies CRC Generation opcodes are supported. Opcodes 
are:
0x81 - CRC-32 Generation
0x82 - CRC-32 Generation & Test
0x83 - CRC-32 Generation & Store
Notes:
When this bit is zero, the DMA engine will abort if it encounters a 
descriptor with these opcodes.
0:0
RO
0x1
page_break:
If set, specifies a transfer crossing physical pages is supported.
Notes:
When this bit is zero, software must not set SPBrk nor DPBrk bits 
in the DMA descriptor and the DMA engine generates an error if 
either of those bits are set
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x14
Bit
Attr
Default
Description
15:0
RO
0x100
dcaregptr:
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x10
Bit
Attr
Default
Description
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