Intel E7-8891 v2 CM8063601377422 User Manual
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
DMA Compatibility Register.
DMA Channel Command Register.
Any Error Abort Enable. This bit enables an abort operation when any error is
encountered during the DMA transfer. When the abort occurs, the DMA
channel generates an interrupt and a completion update as per the Error
Interrupt Enable and Error Completion Enable bits. When this bit is reset,
only affiliated errors cause the DMA channel to abort.This field is RW if
CHANCNT register is 1 otherwise this register is RO.
Error Completion Enable. This bit enables a completion write to the address
specified in the CHANCMP register upon encountering an error during the
DMA transfer. If Any Error Abort is not set, then unaffiliated errors do not
cause a completion write.This field is RW if CHANCNT register is 1 otherwise
this register is RO.
Interrupt Disable. Upon completing a descriptor, if an interrupt is specified
for that descriptor and this bit is reset, then the DMA channel generates an
interrupt and sets this bit. The choice between MSI or legacy interrupt mode
is determined with the MSICTRL register. Legacy interrupts are further gated
through intxDisable in thePCICMD register of the Intel® Quick Data DMA PCI
configuration space. The controlling process can reenable this channel’s
interrupt by writing a one to this bit, which clears the bit. Writing a zero has
no effect. Thus, each time this bit is reset, it enables the DMA channel to
generate one interrupt.
Compatible with version 3 Intel® Quick Data spec
Compatible with version 2 Intel® Quick Data spec
Not compatible with version 1