Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
341
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.5.13 DMA_COMP
DMA Compatibility Register.
14.5.14 CHANCMD
DMA Channel Command Register.
3:3
RW_L
0x0
anyerr_abrt_en:
Any Error Abort Enable. This bit enables an abort operation when any error is 
encountered during the DMA transfer. When the abort occurs, the DMA 
channel generates an interrupt and a completion update as per the Error 
Interrupt Enable and Error Completion Enable bits. When this bit is reset, 
only affiliated errors cause the DMA channel to abort.This field is RW if 
CHANCNT register is 1 otherwise this register is RO.
2:2
RW_L
0x0
err_cmp_en:
Error Completion Enable. This bit enables a completion write to the address 
specified in the CHANCMP register upon encountering an error during the 
DMA transfer. If Any Error Abort is not set, then unaffiliated errors do not 
cause a completion write.This field is RW if CHANCNT register is 1 otherwise 
this register is RO.
1:1
RV
-
Reserved. 
0:0
RW1C
0x0
intp_dis:
Interrupt Disable. Upon completing a descriptor, if an interrupt is specified 
for that descriptor and this bit is reset, then the DMA channel generates an 
interrupt and sets this bit. The choice between MSI or legacy interrupt mode 
is determined with the MSICTRL register. Legacy interrupts are further gated 
through intxDisable in thePCICMD register of the Intel® Quick Data DMA PCI 
configuration space. The controlling process can reenable this channel’s 
interrupt by writing a one to this bit, which clears the bit. Writing a zero has 
no effect. Thus, each time this bit is reset, it enables the DMA channel to 
generate one interrupt.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x80
Bit
Attr
Default
Description
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x82
Bit
Attr
Default
Description
15:3
RV
-
Reserved. 
2:2
RO
0x1
v3_compatibility:
Compatible with version 3 Intel® Quick Data spec
1:1
RO
0x1
v2_compatibility:
Compatible with version 2 Intel® Quick Data spec
0:0
RO
0x0
v1_compatibility:
Not compatible with version 1
downloadlike
ArtboardArtboardArtboard
Report Bug