Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
351
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
39:32
RW
0x80
tag_map_4:
This field is used by the Intel® Quick Data DMA engine to populate Tag field 
bit 4 of the memory write transaction it issues with either 1, 0, or a selected 
APICID bit.
[7:6]
00: Tag[4] = Tag_Map_4[0]
01: Tag[4] = APICID[ Tag_Map_4[3:0] ]
10: Tag[4] = NOT( APICID [Tag_Map_4[3:0] ] )
11: reserved
31:24
RW
0x80
tag_map_3:
This field is used by the Intel® Quick Data DMA engine to populate Tag field 
bit 3 of the memory write transaction it issues with either 1, 0, or a selected 
APICID bit.
[7:6]
00: Tag[3]  = Tag_Map_3[0]
01: Tag[3] = APICID[ Tag_Map_3[3:0] ]
10: Tag[3]  = NOT( APICID[ Tag_Map_3[3:0] ] )
11: reserved
23:16
RW
0x80
tag_map_2:
This field is used by the Intel® Quick Data DMA engine to populate Tag field 
bit 2 of the memory write transaction it issues with either 1, 0, or a selected 
APICID bit.
[7:6]
00: Tag[2]  = Tag_Map_2[0]
01: Tag[2] = APICID[ Tag_Map_2[3:0] ]
10: Tag[2]  = NOT( APICID[ Tag_Map_2[3:0] ] )
11: reserved
15:8
RW
0x80
tag_map_1:
This field is used by the Intel® Quick Data DMA engine to populate Tag field 
bit 1 of the memory write transaction it issues with either 1, 0, or a selected 
APICID bit.
[7:6]
00: Tag[1]  = Tag_Map_1[0]
01: Tag[1] = APICID[ Tag_Map_1[3:0] ]
10: Tag[1]  = NOT( APICID[ Tag_Map_1[3:0] ] )
11: reserved
7:0
RW
0x80
tag_map_0:
This field is used by the Intel® Quick Data DMA engine to populate Tag field 
bit 0 of the memory write transaction it issues with either 1, 0, or a selected 
APICID bit.
[7:6]
00: Tag[0] = Tag_Map_0[0]
01: Tag[0] = APICID[ Tag_Map_0[3:0] ]
10: Tag[0] = NOT (APICID[ Tag_Map_0[3:0] ] )
11: reserved
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x110
Bit
Attr
Default
Description
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