Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
380
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.6.46 VTUNCERRMSK
Intel
®
VT-d Uncorrectable Error Mask.
Mask out error reporting to IIO. Bit 31 should always be set to 1. We recommend that 
the other bits be left as zero so these internal errors are reported out.
Setting bits will not prevent any error collecting INSIDE of Intel
®
VT-d in the 
Intel
®
VT-d Fault Recording Registers. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x1ac
Bit
Attr
Default
Description
31:31
RWS
0x1
vtderr_msk:
This bit should be set to 1 by BIOS. It is highly recommended that this bit is 
never set to 0.
If Intel
®
VT-d errors are configured to be fatal, leaving this bit set to 0 will 
cause Fatal errors to be reported when devices send illegal requests. This is 
generally undesirable.
30:9
RV
-
Reserved1:
Reserved.
8:8
RWS
0x0
protmemviol_msk:
Protected memory region space violated mask
7:7
RWS
0x0
miscerrm:
6:6
RWS
0x0
unsucc_ci_rdcp_msk:
Unsuccessful status received in the coherent interface read completion 
mask.
5:5
RWS
0x0
perr_tlb1_msk:
TLB1 Parity Error mask
4:4
RWS
0x0
perr_tlb0_msk:
TLB0 Parity Error mask
3:3
RWS
0x0
perr_l3_lookup_msk:
Data Parity error while doing a L3 lookup mask
2:2
RWS
0x0
perr_l2_lookup_msk:
Data Parity error while doing a L2 lookup mask
1:1
RWS
0x0
perr_l1_lookup_msk:
Data Parity error while doing a L1 lookup mask
0:0
RWS
0x0
perr_context_cache_msk:
Data Parity error while doing a context cache lookup mask.
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